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authorKenneth Graunke <[email protected]>2016-01-25 15:23:24 -0800
committerKenneth Graunke <[email protected]>2017-07-13 19:56:49 -0700
commit2a5e4f15efb7be113cbc310bb7d809578153953d (patch)
treef7e17f18874f67b479e71f23559712d0e8e97d9b /src
parent8ec5a4e4a4a32f4de351c5fc2bf0eb615b6eef1b (diff)
i965: Require a UBO offset alignment of 32 bytes.
Soon, we're going to start providing UBO data to shaders as push constants, rather than requiring them to issue pull loads. The 3DSTATE_CONSTANT_* commands require 32 byte aligned pointers. So, we need to increase this from 16 to 32. Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index d8f187ff7e7..b23e811f305 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -614,8 +614,11 @@ brw_initialize_context_constants(struct brw_context *brw)
* the element in the buffer."
*
* However, unaligned accesses are slower, so enforce buffer alignment.
+ *
+ * In order to push UBO data, 3DSTATE_CONSTANT_XS imposes an additional
+ * restriction: the start of the buffer needs to be 32B aligned.
*/
- ctx->Const.UniformBufferOffsetAlignment = 16;
+ ctx->Const.UniformBufferOffsetAlignment = 32;
/* ShaderStorageBufferOffsetAlignment should be a cacheline (64 bytes) so
* that we can safely have the CPU and GPU writing the same SSBO on