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authorAxel Davy <[email protected]>2015-01-07 11:12:56 +0100
committerAxel Davy <[email protected]>2015-02-06 00:07:18 +0100
commit70a523818f08f97b6d51f156dca383cfcab8efab (patch)
treea4ed73db87b5b844b8e2d36174de6b1fb5c14d19 /src
parenta249c7a161cdbb995b17195f1af88ed14f69f8b6 (diff)
st/nine: Declare constants only up to the maximum needed.
Previously 276 constants were declared everytime. This patch makes shaders declare constants up to the maximum constant needed and moves the moment we print the TGSI shader after the moment we declare the constants. This is needed for r500, since when indirect addressing is used, it cannot reduce the amount of constants needed, and that it is restricted to 256 constant slots. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Axel Davy <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/state_trackers/nine/nine_shader.c38
1 files changed, 11 insertions, 27 deletions
diff --git a/src/gallium/state_trackers/nine/nine_shader.c b/src/gallium/state_trackers/nine/nine_shader.c
index 3d3dcf3f6b4..b0dd07f820d 100644
--- a/src/gallium/state_trackers/nine/nine_shader.c
+++ b/src/gallium/state_trackers/nine/nine_shader.c
@@ -620,24 +620,6 @@ tx_src_scalar(struct ureg_dst dst)
return src;
}
-/* Need to declare all constants if indirect addressing is used,
- * otherwise we could scan the shader to determine the maximum.
- * TODO: It doesn't really matter for nv50 so I won't do the scan,
- * but radeon drivers might care, if they don't infer it from TGSI.
- */
-static void
-tx_decl_constants(struct shader_translator *tx)
-{
- unsigned i, n = 0;
-
- for (i = 0; i < NINE_MAX_CONST_F; ++i)
- ureg_DECL_constant(tx->ureg, n++);
- for (i = 0; i < NINE_MAX_CONST_I; ++i)
- ureg_DECL_constant(tx->ureg, n++);
- for (i = 0; i < (NINE_MAX_CONST_B / 4); ++i)
- ureg_DECL_constant(tx->ureg, n++);
-}
-
static INLINE void
tx_temp_alloc(struct shader_translator *tx, INT idx)
{
@@ -3067,7 +3049,7 @@ nine_translate_shader(struct NineDevice9 *device, struct nine_shader_info *info)
struct shader_translator *tx;
HRESULT hr = D3D_OK;
const unsigned processor = tgsi_processor_from_type(info->type);
- unsigned slot_max;
+ unsigned s, slot_max;
user_assert(processor != ~0, D3DERR_INVALIDCALL);
@@ -3095,7 +3077,6 @@ nine_translate_shader(struct NineDevice9 *device, struct nine_shader_info *info)
hr = E_OUTOFMEMORY;
goto out;
}
- tx_decl_constants(tx);
tx->native_integers = GET_SHADER_CAP(INTEGERS);
tx->inline_subroutines = !GET_SHADER_CAP(SUBROUTINES);
@@ -3134,13 +3115,6 @@ nine_translate_shader(struct NineDevice9 *device, struct nine_shader_info *info)
if (IS_VS && !ureg_dst_is_undef(tx->regs.oPts))
info->point_size = TRUE;
- if (debug_get_bool_option("NINE_TGSI_DUMP", FALSE)) {
- unsigned count;
- const struct tgsi_token *toks = ureg_get_tokens(tx->ureg, &count);
- tgsi_dump(toks, 0);
- ureg_free_tokens(toks);
- }
-
/* record local constants */
if (tx->num_lconstf && tx->indirect_const_access) {
struct nine_range *ranges;
@@ -3210,6 +3184,16 @@ nine_translate_shader(struct NineDevice9 *device, struct nine_shader_info *info)
info->const_float_slots;
info->const_used_size = sizeof(float[4]) * slot_max; /* slots start from 1 */
+ for (s = 0; s < slot_max; s++)
+ ureg_DECL_constant(tx->ureg, s);
+
+ if (debug_get_bool_option("NINE_TGSI_DUMP", FALSE)) {
+ unsigned count;
+ const struct tgsi_token *toks = ureg_get_tokens(tx->ureg, &count);
+ tgsi_dump(toks, 0);
+ ureg_free_tokens(toks);
+ }
+
info->cso = ureg_create_shader_and_destroy(tx->ureg, device->pipe);
if (!info->cso) {
hr = D3DERR_DRIVERINTERNALERROR;