diff options
| author | Kenneth Graunke <[email protected]> | 2012-01-07 19:32:23 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2012-01-09 21:45:09 -0800 |
| commit | 647b890e7d2fe628812017fd10a6a68fa9e4da8b (patch) | |
| tree | 15ced559163afb616666288d19aea7a97bf9e986 /src | |
| parent | ef034f109427f1a8d31dbe10beed825881130f6b (diff) | |
i965: Update dirty bit comments for the gen7_ps_state atom.
CACHE_NEW_SAMPLER doesn't cover max_wm_threads, but it does cover
brw->sampler.count. BRW_NEW_PS_BINDING_TABLE is obvious, but it's
probably worth adding a comment anyway.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_state.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 93c4440e00d..260d2e221f0 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -101,6 +101,7 @@ upload_ps_state(struct brw_context *brw) struct intel_context *intel = &brw->intel; uint32_t dw2, dw4, dw5; + /* BRW_NEW_PS_BINDING_TABLE */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2)); OUT_BATCH(brw->bind.bo_offset); @@ -143,6 +144,7 @@ upload_ps_state(struct brw_context *brw) dw2 = dw4 = dw5 = 0; + /* CACHE_NEW_SAMPLER */ dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Use ALT floating point mode for ARB fragment programs, because they @@ -151,7 +153,6 @@ upload_ps_state(struct brw_context *brw) if (intel->ctx.Shader.CurrentFragmentProgram == NULL) dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT; - /* CACHE_NEW_SAMPLER */ dw4 |= (brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT; /* CACHE_NEW_WM_PROG */ |