diff options
| author | Chris Forbes <[email protected]> | 2014-02-02 22:00:18 +1300 |
|---|---|---|
| committer | Chris Forbes <[email protected]> | 2014-02-08 10:32:24 +1300 |
| commit | 0c14c5c62a1b4648381c05f024db730e4a0f90c5 (patch) | |
| tree | 9e2dc850cb738f233b8e042ba10667d09c3f06b4 /src | |
| parent | 31d1077dd2f0fec34ac221168943cecc8c9afbf0 (diff) | |
i965: Enable ARB_texture_gather for one component on Gen6.
Signed-off-by: Chris Forbes <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_extensions.c | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 1879abe5605..021287ee234 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -374,6 +374,8 @@ brw_initialize_context_constants(struct brw_context *brw) if (brw->gen >= 7) ctx->Const.MaxProgramTextureGatherComponents = 4; + else if (brw->gen == 6) + ctx->Const.MaxProgramTextureGatherComponents = 1; ctx->Const.MinLineWidth = 1.0; ctx->Const.MinLineWidthAA = 1.0; diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index a0fd354f2cb..eb3f2c7d087 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -270,6 +270,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_texture_multisample = true; ctx->Extensions.ARB_sample_shading = true; ctx->Extensions.ARB_vertex_type_10f_11f_11f_rev = true; + ctx->Extensions.ARB_texture_gather = true; /* Test if the kernel has the ioctl. */ if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0) @@ -284,7 +285,6 @@ intelInitExtensions(struct gl_context *ctx) } if (brw->gen >= 7) { - ctx->Extensions.ARB_texture_gather = true; ctx->Extensions.ARB_conservative_depth = true; ctx->Extensions.AMD_vertex_shader_layer = true; if (can_do_pipelined_register_writes(brw)) { |