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authorJason Ekstrand <[email protected]>2017-05-15 13:27:16 -0700
committerJason Ekstrand <[email protected]>2017-05-26 07:58:01 -0700
commitc19150af5cce3ce3a50b818e0869064a26a62f62 (patch)
treefd87e9224b67b9b73bc83af179d834b758664c10 /src
parent441cd7a81d6fb90dacf8ae441b438d9fe7db19eb (diff)
i965: Use blorp_copy for doing r8 stencil updates on HSW
The blorp_copy entrypoint is designed for doing memcpy like operations which is what we need to do here while blorp_blit is for handling format conversion and scaling. Using blorp_copy is much simpler and prevents us from getting formats wrong. While we're here, we get rid of the layers_per_blit thing since stencil always uses interleaved MSAA. Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c19
1 files changed, 4 insertions, 15 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index db0a3975279..24d01aa32a9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2397,25 +2397,14 @@ intel_update_r8stencil(struct brw_context *brw,
for (int level = src->first_level; level <= src->last_level; level++) {
const unsigned depth = src->level[level].depth;
- const int layers_per_blit =
- (dst->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
- dst->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
- dst->num_samples : 1;
for (unsigned layer = 0; layer < depth; layer++) {
- brw_blorp_blit_miptrees(brw,
+ brw_blorp_copy_miptrees(brw,
src, level, layer,
- src->format, SWIZZLE_X,
- dst, level, layers_per_blit * layer,
- MESA_FORMAT_R_UNORM8,
- 0, 0,
+ dst, level, layer,
+ 0, 0, 0, 0,
minify(src->logical_width0, level),
- minify(src->logical_height0, level),
- 0, 0,
- minify(dst->logical_width0, level),
- minify(dst->logical_height0, level),
- GL_NEAREST, false, false /*mirror x, y*/,
- false, false /* decode/encode srgb */);
+ minify(src->logical_height0, level));
}
}