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authorFrancisco Jerez <currojerez@riseup.net>2017-04-12 16:54:49 -0700
committerFrancisco Jerez <currojerez@riseup.net>2017-04-14 14:56:08 -0700
commit92649a3e6756465b3961cf05910cda93a69c7790 (patch)
treeea6944e4b1a9e1bd11577434d1c2fadd04d59fdd /src
parent6e3265eae533a1bff4f23a4508c5d8e9ab23164d (diff)
i965/vec4: fix assert to detect SIMD lowered DF instructions in IVB
On IVB, DF instructions have lowered the SIMD width to 4 but the exec_size will be later doubled. Fix the assert to avoid crashing in this case. Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> [ Francisco Jerez: Simplify assert. Except for the 'inst->group % 4 == 0' part the assertion was redundant with the previous assertion. ] Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'src')
-rw-r--r--src/intel/compiler/brw_vec4_generator.cpp6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index 5be4ef7fd4b..09081588400 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1524,11 +1524,7 @@ generate_code(struct brw_codegen *p,
brw_set_default_acc_write_control(p, inst->writes_accumulator);
assert(inst->group % inst->exec_size == 0);
- assert(inst->group % 8 == 0 ||
- inst->dst.type == BRW_REGISTER_TYPE_DF ||
- inst->src[0].type == BRW_REGISTER_TYPE_DF ||
- inst->src[1].type == BRW_REGISTER_TYPE_DF ||
- inst->src[2].type == BRW_REGISTER_TYPE_DF);
+ assert(inst->group % 4 == 0);
unsigned exec_size = inst->exec_size;
if (devinfo->gen == 7 &&