diff options
| author | Anuj Phogat <[email protected]> | 2017-11-10 14:22:18 -0800 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2017-11-14 13:23:18 -0800 |
| commit | 72a239266b84033e539283d50ca0b3c50e630463 (patch) | |
| tree | 6513ea97eabec5aadae41604d815ba368bda53ab /src | |
| parent | aacf1943c0a13b8ec565d9f256552608d35c3b4a (diff) | |
intel/genxml: Add Cache Mode SubSlice Register to gen10.xml
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Rafael Antognolli <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/genxml/gen10.xml | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index a7ae49ae659..a6b8f48fda5 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -3752,4 +3752,16 @@ <field name="Color Compression Disable Mask" start="31" end="31" type="bool"/> </register> + <register name="CACHE_MODE_SS" length="1" num="0x0e420"> + <field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool"/> + <field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool"/> + <field name="Float Blend Optimization Enable" start="4" end="4" type="bool"/> + <field name="Per Sample Blend Opt Disable" start="11" end="11" type="bool"/> + + <field name="Instruction Level 1 Cache Disable Mask" start="16" end="16" type="bool"/> + <field name="Instruction Level 1 Cache and In-Flight Queue Disable Mask" start="17" end="17" type="bool"/> + <field name="Float Blend Optimization Enable Mask" start="20" end="20" type="bool"/> + <field name="Per Sample Blend Opt Disable Mask" start="27" end="27" type="bool"/> + </register> + </genxml> |