diff options
| author | Danylo Piliaiev <[email protected]> | 2019-03-25 14:15:27 +0200 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2019-04-16 09:42:08 +0000 |
| commit | 04508f57d1d36587f3cc048f0f5dae0611f9330c (patch) | |
| tree | 21bc629a1cfc41c3884466600b19a7e786310641 /src | |
| parent | 9b2473c7a4427371f9c7ab07ee3c4408b9995207 (diff) | |
intel/compiler: Do not reswizzle dst if instruction writes to flag register
If we write to the flag register changing the swizzle would change
what channels are written to the flag register.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110201
Fixes: 4cd1a0be
Signed-off-by: Danylo Piliaiev <[email protected]>
Reviewed-by: <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index bb8b554c852..7d60665b621 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -1154,6 +1154,12 @@ vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo, if (devinfo->gen == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW) return false; + /* If we write to the flag register changing the swizzle would change + * what channels are written to the flag register. + */ + if (writes_flag()) + return false; + /* We can't swizzle implicit accumulator access. We'd have to * reswizzle the producer of the accumulator value in addition * to the consumer (i.e. both MUL and MACH). Just skip this. |