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authorPaul Berry <[email protected]>2012-05-09 16:00:43 -0700
committerPaul Berry <[email protected]>2012-05-25 08:45:11 -0700
commitb08545199ac8a01392a805f158d22cc03060a6fb (patch)
treeeaa2d5aa5321ef9587fe5f9821a9ee58d0af2a42 /src
parent1c73c705fadf164d61003415e3380f2d06f2e7b3 (diff)
i965/blorp: Enable blorp blits on Gen7.
Gen7 support for blorp (blits using the render bath) now works for non-MSAA purposes. This patch enables it. Since blorp operations re-use the logic for HiZ ops, this required adding a case to the switch statement in gen7_blorp_emit_wm_config(), to allow for the case where no HiZ op is being performed. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp_blit.cpp4
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp2
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 47452b8d64d..10d94a681d7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -187,8 +187,8 @@ brw_blorp_framebuffer(struct intel_context *intel,
GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
GLbitfield mask, GLenum filter)
{
- /* BLORP is only supported on Gen6. TODO: implement on Gen7. */
- if (intel->gen != 6)
+ /* BLORP is not supported before Gen6. */
+ if (intel->gen < 6)
return mask;
static GLbitfield buffer_bits[] = {
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 04548bf63b8..9e1aa4b8d94 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -416,6 +416,8 @@ gen7_blorp_emit_wm_config(struct brw_context *brw,
case GEN6_HIZ_OP_HIZ_RESOLVE:
dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
break;
+ case GEN6_HIZ_OP_NONE:
+ break;
default:
assert(0);
break;