diff options
| author | Kenneth Graunke <[email protected]> | 2014-02-19 17:20:11 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-02-20 15:50:08 -0800 |
| commit | 3663bbe773187dee341556ef29e58b1143ef2f5c (patch) | |
| tree | 2a31e007e22c6f1ece215b726da3273ea94eee59 /src | |
| parent | e3823147a5f5e9c6234d8e89a55b79e8e9eb164c (diff) | |
i965: Create a hardware context before initializing state module.
brw_init_state() calls brw_upload_initial_gpu_state(). If hardware
contexts are enabled (brw->hw_ctx != NULL), this will upload some
initial invariant state for the GPU. Without hardware contexts, we
rely on this state being uploaded via atoms that subscribe to the
BRW_NEW_CONTEXT bit.
Commit 46d3c2bf4ddd227193b98861f1e632498fe547d8 accidentally moved
the call to brw_init_state() before creating a hardware context.
This meant brw_upload_initial_gpu_state would always early return.
Except on Gen6+, we stopped uploading the initial GPU state via
state atoms, so it never happened.
Fixes a regression since 46d3c2bf4ddd227193b98861f1e632498fe547d8.
Cc: "10.0 10.1" <[email protected]>
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 580009248a7..9791a49749a 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -700,12 +700,6 @@ brwCreateContext(gl_api api, intel_batchbuffer_init(brw); - brw_init_state(brw); - - intelInitExtensions(ctx); - - intel_fbo_init(brw); - if (brw->gen >= 6) { /* Create a new hardware context. Using a hardware context means that * our GPU state will be saved/restored on context switch, allowing us @@ -723,6 +717,12 @@ brwCreateContext(gl_api api, } } + brw_init_state(brw); + + intelInitExtensions(ctx); + + intel_fbo_init(brw); + brw_init_surface_formats(brw); if (brw->is_g4x || brw->gen >= 5) { |