i965: Use Ivybridge's "Legacy Data Port" for reads/writes.

Using the constant cache for reads isn't going to work for scratch
reads (variably-indexed arrays or register spills), as these aren't
constant at all.

Also, in the new VS backend, use the proper message number for OWord
Dual Block Write messages.  It's now 10, instead of 9.

+205 piglits.

NOTE: This is a candidate for the 7.11 branch.

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>

3 files changed, 16 insertions, 5 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 21a115b799b..dee4cef18ed 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -758,6 +758,8 @@ enum opcode {
 #define GEN6_MESSAGE_TARGET_DP_RENDER_CACHE   5
 #define GEN6_MESSAGE_TARGET_DP_CONST_CACHE    9
 
+#define GEN7_MESSAGE_TARGET_DP_DATA_CACHE     10
+
 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
 #define BRW_SAMPLER_RETURN_FORMAT_UINT32      2
 #define BRW_SAMPLER_RETURN_FORMAT_SINT32      3
@@ -855,6 +857,9 @@ enum opcode {
 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE               13
 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE       14
 
+/* GEN7 */
+#define GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE          10
+
 #define BRW_MATH_FUNCTION_INV                              1
 #define BRW_MATH_FUNCTION_LOG                              2
 #define BRW_MATH_FUNCTION_EXP                              3
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 66649a745eb..7f6ed6810bf 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -546,6 +546,13 @@ brw_set_dp_write_message(struct brw_compile *p,
    brw_set_src1(p, insn, brw_imm_ud(0));
 
    if (intel->gen >= 7) {
+      /* Use the Render Cache for RT writes; otherwise use the Data Cache */
+      unsigned sfid = GEN7_MESSAGE_TARGET_DP_DATA_CACHE;
+      if (msg_type == GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE)
+	 sfid = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
+
+      insn->header.destreg__conditionalmod = sfid;
+
       insn->bits3.gen7_dp.binding_table_index = binding_table_index;
       insn->bits3.gen7_dp.msg_control = msg_control;
       insn->bits3.gen7_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;
@@ -554,9 +561,6 @@ brw_set_dp_write_message(struct brw_compile *p,
       insn->bits3.gen7_dp.response_length = response_length;
       insn->bits3.gen7_dp.msg_length = msg_length;
       insn->bits3.gen7_dp.end_of_thread = end_of_thread;
-
-      /* We always use the render cache for write messages */
-      insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
    } else if (intel->gen == 6) {
       insn->bits3.gen6_dp.binding_table_index = binding_table_index;
       insn->bits3.gen6_dp.msg_control = msg_control;
@@ -618,7 +622,7 @@ brw_set_dp_read_message(struct brw_compile *p,
       insn->bits3.gen7_dp.response_length = response_length;
       insn->bits3.gen7_dp.msg_length = msg_length;
       insn->bits3.gen7_dp.end_of_thread = 0;
-      insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_CONST_CACHE;
+      insn->header.destreg__conditionalmod = GEN7_MESSAGE_TARGET_DP_DATA_CACHE;
    } else if (intel->gen == 6) {
       uint32_t target_function;
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 09e7cfbc0da..e93e3193d2a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -450,7 +450,9 @@ vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 
    uint32_t msg_type;
 
-   if (intel->gen >= 6)
+   if (intel->gen >= 7)
+      msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
+   else if (intel->gen == 6)
       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
    else
       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;