radeon/llvm: More comments and cleanups

22 files changed, 190 insertions, 163 deletions

diff --git a/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp b/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp
index 8e82b8438bb..1a3cf014d51 100644
--- a/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp
@@ -19,21 +19,20 @@
 using namespace llvm;
 
 namespace {
-  class AMDGPUConvertToISAPass : public MachineFunctionPass {
 
-  private:
-    static char ID;
-    TargetMachine &TM;
+class AMDGPUConvertToISAPass : public MachineFunctionPass {
 
-    void lowerFLT(MachineInstr &MI);
+private:
+  static char ID;
+  TargetMachine &TM;
 
-  public:
-    AMDGPUConvertToISAPass(TargetMachine &tm) :
-      MachineFunctionPass(ID), TM(tm) { }
+public:
+  AMDGPUConvertToISAPass(TargetMachine &tm) :
+    MachineFunctionPass(ID), TM(tm) { }
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
+  virtual bool runOnMachineFunction(MachineFunction &MF);
+};
 
-  };
 } // End anonymous namespace
 
 char AMDGPUConvertToISAPass::ID = 0;
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 2bdc8a759f2..8d4207f24d4 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -24,8 +24,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
 
 void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI,
     MachineFunction * MF, MachineRegisterInfo & MRI,
-    const struct TargetInstrInfo * TII, unsigned reg) const
+    const TargetInstrInfo * TII, unsigned reg) const
 {
-  AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg()); 
+  AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg());
 }
 
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
index 1b3f71006e2..16adf1b32bb 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
@@ -22,8 +22,15 @@ namespace llvm {
 class AMDGPUTargetLowering : public AMDILTargetLowering
 {
 protected:
+
+  /// addLiveIn - This functions adds reg to the live in list of the entry block
+  /// and emits a copy from reg to MI.getOperand(0).
+  ///
+  //  Some registers are loaded with values before the program
+  /// begins to execute.  The loading of these values is modeled with pseudo
+  /// instructions which are lowered using this function. 
   void addLiveIn(MachineInstr * MI, MachineFunction * MF,
-                 MachineRegisterInfo & MRI, const struct TargetInstrInfo * TII,
+                 MachineRegisterInfo & MRI, const TargetInstrInfo * TII,
 		 unsigned reg) const;
 
 public:
@@ -31,6 +38,6 @@ public:
 
 };
 
-} /* End namespace llvm */
+} // End namespace llvm
 
-#endif /* AMDGPUISELLOWERING_H */
+#endif // AMDGPUISELLOWERING_H
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
index ecd8ac90526..2d683c7bcee 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
@@ -76,12 +76,12 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction
   const AMDGPURegisterInfo & RI = getRegisterInfo();
   unsigned ISAOpcode = getISAOpcode(MI.getOpcode());
 
-  /* Create the new instruction */
+  // Create the new instruction
   newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(ISAOpcode));
 
   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
     MachineOperand &MO = MI.getOperand(i);
-    /* Convert dst regclass to one that is supported by the ISA */
+    // Convert dst regclass to one that is supported by the ISA
     if (MO.isReg() && MO.isDef()) {
       if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
         const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
@@ -92,7 +92,7 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction
         MRI.setRegClass(MO.getReg(), newRegClass);
       }
     }
-    /* Add the operand to the new instruction */
+    // Add the operand to the new instruction
     newInstr.addOperand(MO);
   }
 
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
index 930b41e7191..0f3698930a9 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file contains the definitoin of a TargetInstrInfo class that is common
+// This file contains the definition of a TargetInstrInfo class that is common
 // to all AMD GPUs.
 //
 //===----------------------------------------------------------------------===//
@@ -37,8 +37,12 @@ public:
 
   virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
 
+  /// getISAOpcode - This function takes an AMDIL opcode as an argument and
+  /// returns an equivalent ISA opcode.
   virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
 
+  /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
+  /// MachineInstr
   virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
     DebugLoc DL) const;
 
diff --git a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp b/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
index 2e455fea8ab..42374ef1254 100644
--- a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
+++ b/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
@@ -23,22 +23,24 @@
 using namespace llvm;
 
 namespace {
-  class AMDGPULowerInstructionsPass : public MachineFunctionPass {
 
-  private:
-    static char ID;
-    TargetMachine &TM;
-    void lowerVCREATE_v4(MachineInstr &MI, MachineBasicBlock::iterator I,
-                              MachineBasicBlock &MBB, MachineFunction &MF);
+class AMDGPULowerInstructionsPass : public MachineFunctionPass {
 
-  public:
-    AMDGPULowerInstructionsPass(TargetMachine &tm) :
-      MachineFunctionPass(ID), TM(tm) { }
+private:
+  static char ID;
+  TargetMachine &TM;
+  void lowerVCREATE_v4(MachineInstr &MI, MachineBasicBlock::iterator I,
+                            MachineBasicBlock &MBB, MachineFunction &MF);
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
+public:
+  AMDGPULowerInstructionsPass(TargetMachine &tm) :
+    MachineFunctionPass(ID), TM(tm) { }
 
-  };
-} /* End anonymous namespace */
+  virtual bool runOnMachineFunction(MachineFunction &MF);
+
+};
+
+} // End anonymous namespace
 
 char AMDGPULowerInstructionsPass::ID = 0;
 
diff --git a/src/gallium/drivers/radeon/AMDGPURegisterInfo.h b/src/gallium/drivers/radeon/AMDGPURegisterInfo.h
index d545c06f69e..5863807a139 100644
--- a/src/gallium/drivers/radeon/AMDGPURegisterInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPURegisterInfo.h
@@ -19,21 +19,24 @@
 
 namespace llvm {
 
-  class AMDGPUTargetMachine;
-  class TargetInstrInfo;
+class AMDGPUTargetMachine;
+class TargetInstrInfo;
 
-  struct AMDGPURegisterInfo : public AMDILRegisterInfo
-  {
-    AMDGPUTargetMachine &TM;
-    const TargetInstrInfo &TII;
+struct AMDGPURegisterInfo : public AMDILRegisterInfo
+{
+  AMDGPUTargetMachine &TM;
+  const TargetInstrInfo &TII;
 
-    AMDGPURegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+  AMDGPURegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
 
-    virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
 
-    virtual const TargetRegisterClass *
+  /// getISARegClass - rc is an AMDIL reg class.  This function returns the
+  /// ISA reg class that is equivalent to the given AMDIL reg class.
+  virtual const TargetRegisterClass *
     getISARegClass(const TargetRegisterClass * rc) const = 0;
-  };
+};
+
 } // End namespace llvm
 
 #endif // AMDIDSAREGISTERINFO_H_
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index c1c21abc9c1..5c4d82b6597 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -45,7 +45,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
   mDump(false)
 
 {
-  /* TLInfo uses InstrInfo so it must be initialized after. */
+  // TLInfo uses InstrInfo so it must be initialized after.
   if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
     InstrInfo = new R600InstrInfo(*this);
     TLInfo = new R600TargetLowering(*this);
@@ -63,8 +63,8 @@ bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                               formatted_raw_ostream &Out,
                                               CodeGenFileType FileType,
                                               bool DisableVerify) {
-  /* XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
-   * only using it to access addPassesToGenerateCode() */
+  // XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
+  // only using it to access addPassesToGenerateCode()
   bool fail = LLVMTargetMachine::addPassesToEmitFile(PM, Out, FileType,
                                                      DisableVerify);
   assert(fail);
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.h b/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
index 2428fe638a7..2f60e76299b 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
@@ -54,6 +54,6 @@ public:
                                               bool DisableVerify);
 };
 
-} /* End namespace llvm */
+} // End namespace llvm
 
-#endif /* AMDGPU_TARGET_MACHINE_H */
+#endif // AMDGPU_TARGET_MACHINE_H
diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.cpp b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
index bd8f5eef697..f0621384dbc 100644
--- a/src/gallium/drivers/radeon/AMDGPUUtil.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
@@ -119,7 +119,7 @@ bool AMDGPU::isFCOp(unsigned opcode)
   case AMDIL::CONTINUE_LOGICALNZ_f32:
   case AMDIL::IF_LOGICALNZ_i32:
   case AMDIL::IF_LOGICALZ_f32:
-	case AMDIL::ELSE:
+  case AMDIL::ELSE:
   case AMDIL::ENDIF:
   case AMDIL::ENDLOOP:
   case AMDIL::IF_LOGICALNZ_f32:
@@ -129,16 +129,16 @@ bool AMDGPU::isFCOp(unsigned opcode)
 }
 
 void AMDGPU::utilAddLiveIn(llvm::MachineFunction * MF,
-													 llvm::MachineRegisterInfo & MRI,
-													 const struct llvm::TargetInstrInfo * TII,
-													 unsigned physReg, unsigned virtReg)
+                           llvm::MachineRegisterInfo & MRI,
+                           const llvm::TargetInstrInfo * TII,
+                           unsigned physReg, unsigned virtReg)
 {
     if (!MRI.isLiveIn(physReg)) {
       MRI.addLiveIn(physReg, virtReg);
       MF->front().addLiveIn(physReg);
       BuildMI(MF->front(), MF->front().begin(), DebugLoc(),
-                           TII->get(TargetOpcode::COPY), virtReg)
-            .addReg(physReg);
+              TII->get(TargetOpcode::COPY), virtReg)
+                .addReg(physReg);
     } else {
       MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
     }
diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.h b/src/gallium/drivers/radeon/AMDGPUUtil.h
index 15f2ce57af9..633ea3bf6cf 100644
--- a/src/gallium/drivers/radeon/AMDGPUUtil.h
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.h
@@ -39,7 +39,7 @@ bool isFCOp(unsigned opcode);
 #define MO_FLAG_MASK  (1 << 3)
 
 void utilAddLiveIn(llvm::MachineFunction * MF, llvm::MachineRegisterInfo & MRI,
-    const struct llvm::TargetInstrInfo * TII, unsigned physReg, unsigned virtReg);
+    const llvm::TargetInstrInfo * TII, unsigned physReg, unsigned virtReg);
 
 } // End namespace AMDGPU
 
diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
index 421562255f6..cc1fbb72cf5 100644
--- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
@@ -90,8 +90,6 @@ namespace {
 
   unsigned getHWReg(unsigned regNo) const;
 
-  unsigned getElement(unsigned regNo);
-
 };
 
 } /* End anonymous namespace */
@@ -710,19 +708,5 @@ uint64_t R600CodeEmitter::getMachineOpValue(const MachineInstr &MI,
   }
 }
 
-
-RegElement maskBitToElement(unsigned int maskBit)
-{
-  switch (maskBit) {
-    case WRITE_MASK_X: return ELEMENT_X;
-    case WRITE_MASK_Y: return ELEMENT_Y;
-    case WRITE_MASK_Z: return ELEMENT_Z;
-    case WRITE_MASK_W: return ELEMENT_W;
-    default:
-      assert("Invalid maskBit");
-      return ELEMENT_X;
-  }
-}
-
 #include "AMDILGenCodeEmitter.inc"
 
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.h b/src/gallium/drivers/radeon/R600ISelLowering.h
index fdd552a172d..6296145f668 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.h
+++ b/src/gallium/drivers/radeon/R600ISelLowering.h
@@ -30,6 +30,10 @@ public:
 private:
   const R600InstrInfo * TII;
 
+  /// lowerImplicitParameter - Each OpenCL kernel has nine implicit parameters
+  /// that are stored in the first nine dwords of a Vertex Buffer.  These
+  /// implicit parameters are represented by pseudo instructions, which are
+  /// lowered to VTX_READ instructions by this function. 
   void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
       MachineRegisterInfo & MRI, unsigned dword_offset) const;
 
diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.h b/src/gallium/drivers/radeon/R600RegisterInfo.h
index 89a11f9333b..7525a97d50a 100644
--- a/src/gallium/drivers/radeon/R600RegisterInfo.h
+++ b/src/gallium/drivers/radeon/R600RegisterInfo.h
@@ -19,26 +19,37 @@
 
 namespace llvm {
 
-  class R600TargetMachine;
-  class TargetInstrInfo;
+class R600TargetMachine;
+class TargetInstrInfo;
 
-  struct R600RegisterInfo : public AMDGPURegisterInfo
-  {
-    AMDGPUTargetMachine &TM;
-    const TargetInstrInfo &TII;
+struct R600RegisterInfo : public AMDGPURegisterInfo
+{
+  AMDGPUTargetMachine &TM;
+  const TargetInstrInfo &TII;
 
-    R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+  R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
 
-    virtual BitVector getReservedRegs(const MachineFunction &MF) const;
+  virtual BitVector getReservedRegs(const MachineFunction &MF) const;
+
+  /// getISARegClass - rc is an AMDIL reg class.  This function returns the
+  /// R600 reg class that is equivalent to the given AMDIL reg class.
+  virtual const TargetRegisterClass * getISARegClass(
+    const TargetRegisterClass * rc) const;
+
+  /// getHWRegIndex - get the HW encoding for a register.
+  unsigned getHWRegIndex(unsigned reg) const;
+
+  /// getHWRegChan - get the HW encoding for a register's channel.
+  unsigned getHWRegChan(unsigned reg) const;
 
-    virtual const TargetRegisterClass *
-    getISARegClass(const TargetRegisterClass * rc) const;
-    unsigned getHWRegIndex(unsigned reg) const;
-    unsigned getHWRegChan(unsigned reg) const;
 private:
-    unsigned getHWRegChanGen(unsigned reg) const;
-    unsigned getHWRegIndexGen(unsigned reg) const;
-  };
+  /// getHWRegIndexGen - Generated function returns a register's encoding
+  unsigned getHWRegIndexGen(unsigned reg) const;
+  /// getHWRegChanGen - Generated function returns a register's channel
+  /// encoding.
+  unsigned getHWRegChanGen(unsigned reg) const;
+};
+
 } // End namespace llvm
 
 #endif // AMDIDSAREGISTERINFO_H_
diff --git a/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp b/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp
index 1ef097f7b1e..a2d14b5fb2f 100644
--- a/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp
+++ b/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp
@@ -28,20 +28,22 @@
 using namespace llvm;
 
 namespace {
-  class SIAssignInterpRegsPass : public MachineFunctionPass {
 
-  private:
-    static char ID;
-    TargetMachine &TM;
+class SIAssignInterpRegsPass : public MachineFunctionPass {
 
-  public:
-    SIAssignInterpRegsPass(TargetMachine &tm) :
-      MachineFunctionPass(ID), TM(tm) { }
+private:
+  static char ID;
+  TargetMachine &TM;
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
+public:
+  SIAssignInterpRegsPass(TargetMachine &tm) :
+    MachineFunctionPass(ID), TM(tm) { }
+
+  virtual bool runOnMachineFunction(MachineFunction &MF);
+
+  const char *getPassName() const { return "SI Assign intrpolation registers"; }
+};
 
-    const char *getPassName() const { return "SI Assign intrpolation registers"; }
-  };
 } // End anonymous namespace
 
 char SIAssignInterpRegsPass::ID = 0;
diff --git a/src/gallium/drivers/radeon/SICodeEmitter.cpp b/src/gallium/drivers/radeon/SICodeEmitter.cpp
index 6970d9f0875..1db9764365a 100644
--- a/src/gallium/drivers/radeon/SICodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/SICodeEmitter.cpp
@@ -49,14 +49,24 @@ namespace {
         _OS(OS), TM(NULL) { }
     const char *getPassName() const { return "SI Code Emitter"; }
     bool runOnMachineFunction(MachineFunction &MF);
+
+    /// getMachineOpValue - Return the encoding for MO
     virtual uint64_t getMachineOpValue(const MachineInstr &MI,
                                        const MachineOperand &MO) const;
+
+    /// GPR4AlignEncode - Encoding for when 4 consectuive registers are used 
     virtual unsigned GPR4AlignEncode(const MachineInstr  &MI, unsigned OpNo)
                                                                       const;
+
+    /// GPR2AlignEncode - Encoding for when 2 consecutive registers are used
     virtual unsigned GPR2AlignEncode(const MachineInstr &MI, unsigned OpNo)
                                                                       const;
+    /// i32LiteralEncode - Encode an i32 literal this is used as an operand
+    /// for an instruction in place of a register.
     virtual uint64_t i32LiteralEncode(const MachineInstr &MI, unsigned OpNo)
                                                                       const;
+
+    /// VOPPostEncode - Post-Encoder method for VOP instructions 
     virtual uint64_t VOPPostEncode(const MachineInstr &MI,
                                    uint64_t Value) const;
   };
@@ -174,8 +184,6 @@ void SICodeEmitter::emitInstr(MachineInstr &MI)
     abort();
   }
 
-//  hwInst |= SII->getBinaryCode(MI);
-
   unsigned bytes = SII->getEncodingBytes(MI);
   outputBytes(hwInst, bytes);
 }
@@ -194,8 +202,8 @@ uint64_t SICodeEmitter::getMachineOpValue(const MachineInstr &MI,
     return MO.getImm();
 
   case MachineOperand::MO_FPImmediate:
-    /* XXX: Not all instructions can use inline literals */
-    /* XXX: We should make sure this is a 32-bit constant */
+    // XXX: Not all instructions can use inline literals
+    // XXX: We should make sure this is a 32-bit constant
     return LITERAL_REG | (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
   default:
     llvm_unreachable("Encoding of this operand type is not supported yet.");
@@ -230,9 +238,8 @@ uint64_t SICodeEmitter::i32LiteralEncode(const MachineInstr &MI,
   return LITERAL_REG | (MI.getOperand(OpNo).getImm() << 32);
 }
 
-/* Set the "VGPR" bit for VOP args that can take either a VGPR or a SGPR.
- * XXX: It would be nice if we could handle this without a PostEncode function.
- */
+/// Set the "VGPR" bit for VOP args that can take either a VGPR or a SGPR.
+/// XXX: It would be nice if we could handle this without a PostEncode function.
 uint64_t SICodeEmitter::VOPPostEncode(const MachineInstr &MI,
     uint64_t Value) const
 {
@@ -249,7 +256,7 @@ uint64_t SICodeEmitter::VOPPostEncode(const MachineInstr &MI,
     vgprBitOffset = 0;
   }
 
-  /* Add one to skip over the destination reg operand. */
+  // Add one to skip over the destination reg operand.
   for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
     if (!MI.getOperand(opIdx).isReg()) {
       continue;
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp
index 441a4a07290..e176defcf5d 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -33,7 +33,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
     MachineInstr * MI, MachineBasicBlock * BB) const
 {
-  const struct TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
+  const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
   MachineRegisterInfo & MRI = BB->getParent()->getRegInfo();
   MachineBasicBlock::iterator I = MI;
 
@@ -141,7 +141,7 @@ void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
 void SITargetLowering::lowerUSE_SGPR(MachineInstr *MI,
     MachineFunction * MF, MachineRegisterInfo & MRI) const
 {
-  const struct TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
+  const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
   unsigned dstReg = MI->getOperand(0).getReg();
   int64_t newIndex = MI->getOperand(1).getImm();
   const TargetRegisterClass * dstClass = MRI.getRegClass(dstReg);
diff --git a/src/gallium/drivers/radeon/SIISelLowering.h b/src/gallium/drivers/radeon/SIISelLowering.h
index 229e682ef51..4a1bc38b5f6 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.h
+++ b/src/gallium/drivers/radeon/SIISelLowering.h
@@ -23,6 +23,10 @@ class SITargetLowering : public AMDGPUTargetLowering
 {
   const SIInstrInfo * TII;
 
+  /// AppendS_WAITCNT - Memory reads and writes are syncronized using the
+  /// S_WAITCNT instruction.  This function takes the most conservative
+  /// approach and inserts an S_WAITCNT instruction after every read and
+  /// write.
   void AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB,
               MachineBasicBlock::iterator I) const;
   void LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
diff --git a/src/gallium/drivers/radeon/SIInstrInfo.h b/src/gallium/drivers/radeon/SIInstrInfo.h
index 68940ea3ca4..24f7a56f638 100644
--- a/src/gallium/drivers/radeon/SIInstrInfo.h
+++ b/src/gallium/drivers/radeon/SIInstrInfo.h
@@ -20,48 +20,52 @@
 
 namespace llvm {
 
-  class SIInstrInfo : public AMDGPUInstrInfo {
-  private:
-    const SIRegisterInfo RI;
-    AMDGPUTargetMachine &TM;
+class SIInstrInfo : public AMDGPUInstrInfo {
+private:
+  const SIRegisterInfo RI;
+  AMDGPUTargetMachine &TM;
 
-    MachineInstr * convertABS_f32(MachineInstr & absInstr, MachineFunction &MF,
-                                  DebugLoc DL) const;
+  MachineInstr * convertABS_f32(MachineInstr & absInstr, MachineFunction &MF,
+                                DebugLoc DL) const;
 
-    MachineInstr * convertCLAMP_f32(MachineInstr & clampInstr,
-                                    MachineFunction &MF, DebugLoc DL) const;
+  MachineInstr * convertCLAMP_f32(MachineInstr & clampInstr,
+                                  MachineFunction &MF, DebugLoc DL) const;
 
-  public:
-    explicit SIInstrInfo(AMDGPUTargetMachine &tm);
+public:
+  explicit SIInstrInfo(AMDGPUTargetMachine &tm);
 
-    const SIRegisterInfo &getRegisterInfo() const;
+  const SIRegisterInfo &getRegisterInfo() const;
 
-    virtual void copyPhysReg(MachineBasicBlock &MBB,
+  virtual void copyPhysReg(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, DebugLoc DL,
                            unsigned DestReg, unsigned SrcReg,
                            bool KillSrc) const;
 
-    unsigned getEncodingType(const MachineInstr &MI) const;
+  /// getEncodingType - Returns the encoding type of this instruction.  
+  unsigned getEncodingType(const MachineInstr &MI) const;
 
-    unsigned getEncodingBytes(const MachineInstr &MI) const;
+  /// getEncodingBytes - Returns the size of this instructions encoding in
+  /// number of bytes.
+  unsigned getEncodingBytes(const MachineInstr &MI) const;
 
-    uint64_t getBinaryCode(const MachineInstr &MI, bool encodOpcode = false) const;
-
-    virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
+  /// convertToISA - Convert the AMDIL MachineInstr to a supported SI
+  ///MachineInstr
+  virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
                                         DebugLoc DL) const;
 
-    virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
+  /// getISAOpcode - This function takes an AMDIL opcode as an argument and
+  /// returns an equivalent SI opcode.
+  virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
 
   };
 
 } // End namespace llvm
 
-/* These must be kept in sync with SIInstructions.td and also the
- * InstrEncodingInfo array in SIInstrInfo.cpp.
- *
- * NOTE: This enum is only used to identify the encoding type within LLVM,
- * the actual encoding type that is part of the instruction format is different
- */
+// These must be kept in sync with SIInstructions.td and also the
+// InstrEncodingInfo array in SIInstrInfo.cpp.
+//
+// NOTE: This enum is only used to identify the encoding type within LLVM,
+// the actual encoding type that is part of the instruction format is different
 namespace SIInstrEncodingType {
   enum Encoding {
     EXP = 0,
@@ -87,7 +91,7 @@ namespace SIInstrEncodingType {
 
 namespace SIInstrFlags {
   enum Flags {
-    /* First 4 bits are the instruction encoding */
+    // First 4 bits are the instruction encoding
     NEED_WAIT = 1 << 4
   };
 }
diff --git a/src/gallium/drivers/radeon/SIPropagateImmReads.cpp b/src/gallium/drivers/radeon/SIPropagateImmReads.cpp
index 6a165488831..09a28c605e2 100644
--- a/src/gallium/drivers/radeon/SIPropagateImmReads.cpp
+++ b/src/gallium/drivers/radeon/SIPropagateImmReads.cpp
@@ -21,19 +21,21 @@
 using namespace llvm;
 
 namespace {
-  class SIPropagateImmReadsPass : public MachineFunctionPass {
 
-  private:
-    static char ID;
-    TargetMachine &TM;
+class SIPropagateImmReadsPass : public MachineFunctionPass {
 
-  public:
-    SIPropagateImmReadsPass(TargetMachine &tm) :
-      MachineFunctionPass(ID), TM(tm) { }
+private:
+  static char ID;
+  TargetMachine &TM;
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
-  };
-} /* End anonymous namespace */
+public:
+  SIPropagateImmReadsPass(TargetMachine &tm) :
+    MachineFunctionPass(ID), TM(tm) { }
+
+  virtual bool runOnMachineFunction(MachineFunction &MF);
+};
+
+} // End anonymous namespace
 
 char SIPropagateImmReadsPass::ID = 0;
 
@@ -60,7 +62,7 @@ bool SIPropagateImmReadsPass::runOnMachineFunction(MachineFunction &MF)
         continue;
       }
 
-      /* XXX: Create and use S_MOV_IMM for SREGs */
+      // XXX: Create and use S_MOV_IMM for SREGs
       BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::V_MOV_IMM))
           .addOperand(MI.getOperand(0))
           .addOperand(MI.getOperand(1));
diff --git a/src/gallium/drivers/radeon/SIRegisterInfo.cpp b/src/gallium/drivers/radeon/SIRegisterInfo.cpp
index 2d530a4f022..04e2e17d7ec 100644
--- a/src/gallium/drivers/radeon/SIRegisterInfo.cpp
+++ b/src/gallium/drivers/radeon/SIRegisterInfo.cpp
@@ -40,16 +40,6 @@ unsigned SIRegisterInfo::getBinaryCode(unsigned reg) const
   }
 }
 
-bool SIRegisterInfo::isBaseRegClass(unsigned regClassID) const
-{
-  switch (regClassID) {
-  default: return true;
-  case AMDIL::AllReg_32RegClassID:
-  case AMDIL::AllReg_64RegClassID:
-    return false;
-  }
-}
-
 const TargetRegisterClass *
 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
 {
diff --git a/src/gallium/drivers/radeon/SIRegisterInfo.h b/src/gallium/drivers/radeon/SIRegisterInfo.h
index 77f3261efc5..949a1e2f6b7 100644
--- a/src/gallium/drivers/radeon/SIRegisterInfo.h
+++ b/src/gallium/drivers/radeon/SIRegisterInfo.h
@@ -19,27 +19,31 @@
 
 namespace llvm {
 
-  class AMDGPUTargetMachine;
-  class TargetInstrInfo;
+class AMDGPUTargetMachine;
+class TargetInstrInfo;
 
-  struct SIRegisterInfo : public AMDGPURegisterInfo
-  {
-    AMDGPUTargetMachine &TM;
-    const TargetInstrInfo &TII;
+struct SIRegisterInfo : public AMDGPURegisterInfo
+{
+  AMDGPUTargetMachine &TM;
+  const TargetInstrInfo &TII;
 
-    SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+  SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
 
-    virtual BitVector getReservedRegs(const MachineFunction &MF) const;
-    virtual unsigned getBinaryCode(unsigned reg) const;
+  virtual BitVector getReservedRegs(const MachineFunction &MF) const;
 
-    virtual bool isBaseRegClass(unsigned regClassID) const;
+  /// getBinaryCode - Returns the hardware encoding for a register
+  virtual unsigned getBinaryCode(unsigned reg) const;
 
-    virtual const TargetRegisterClass *
+  /// getISARegClass - rc is an AMDIL reg class.  This function returns the
+  /// SI register class that is equivalent to the given AMDIL register class.
+  virtual const TargetRegisterClass *
     getISARegClass(const TargetRegisterClass * rc) const;
 
-    unsigned getHWRegNum(unsigned reg) const;
+  /// getHWRegNum - Generated function that returns the hardware encoding for
+  /// a register
+  unsigned getHWRegNum(unsigned reg) const;
 
-  };
+};
 
 } // End namespace llvm