diff options
| author | Matt Turner <[email protected]> | 2013-11-16 12:31:26 -0800 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2013-11-20 15:04:52 -0800 |
| commit | 9bbedf6146be6ecad2863fd924c434a2a530c361 (patch) | |
| tree | 1144c8e003ba2c02abc9a2fce1709c4aaa4d8b2e /src | |
| parent | 82bfb45e24c7a19031a19ad1d361c07dd3da4987 (diff) | |
i965/fs: Emit compressed 3-source instructions on Haswell.
For commit 4df56177 Paul discovered that the hardware restriction that
Align16 instructions cannot be compressed was lifted on Haswell. This
has prevented us from emitting compressed three-source instructions.
For added confirmation, the bspec lists a work around called
WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable
since very early Haswell silicon.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index cc58ff2598b..a97a016b8b3 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1404,7 +1404,7 @@ fs_generator::generate_code(exec_list *instructions) case BRW_OPCODE_MAD: assert(brw->gen >= 6); brw_set_access_mode(p, BRW_ALIGN_16); - if (dispatch_width == 16) { + if (dispatch_width == 16 && !brw->is_haswell) { brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_MAD(p, dst, src[0], src[1], src[2]); brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); @@ -1419,7 +1419,7 @@ fs_generator::generate_code(exec_list *instructions) case BRW_OPCODE_LRP: assert(brw->gen >= 6); brw_set_access_mode(p, BRW_ALIGN_16); - if (dispatch_width == 16) { + if (dispatch_width == 16 && !brw->is_haswell) { brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_LRP(p, dst, src[0], src[1], src[2]); brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); @@ -1516,7 +1516,7 @@ fs_generator::generate_code(exec_list *instructions) case BRW_OPCODE_BFE: assert(brw->gen >= 7); brw_set_access_mode(p, BRW_ALIGN_16); - if (dispatch_width == 16) { + if (dispatch_width == 16 && !brw->is_haswell) { brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_BFE(p, dst, src[0], src[1], src[2]); brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); |