diff options
| author | Ben Widawsky <[email protected]> | 2015-07-08 17:04:10 -0700 |
|---|---|---|
| committer | Nanley Chery <[email protected]> | 2015-08-31 10:08:43 -0700 |
| commit | d2e3638ef9e2ddf7e02b9fbe3fa8d40c63ebe5da (patch) | |
| tree | bb0b150467eb4ed58a80ff80bcc99d00b18c1745 /src | |
| parent | 78027c965a50719959df821b7f545db191574724 (diff) | |
i965/chv|skl: Apply sampler bypass w/a
Certain compressed formats require this setting. The docs don't go into much
detail as to why it's needed exactly.
This patch introduces no piglit regressions on gen9 (bsw is untested). Note that
the SKL "regressions" are fixed tests, and the egl_khr_gl_colorspace tests are
WTF. The patch also fixes nothing I can find.
http://otc-mesa-ci.jf.intel.com/job/Leeroy/127820/
v2:
Reworded commit message (Matt); Added piglit results link.
Restructured condition (Matt)
Moved check out to function (Nanley). I left the setting of the bit in the
surface state open coded because it seems to go better with the existing code.
v3:
Use and inline function only in gen8_emit_texture_surface_state() (Matt).
Cc: Matt Turner <[email protected]>
Cc: Nanley Chery <[email protected]>
Signed-off-by: Ben Widawsky <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_surface_state.c | 14 |
2 files changed, 15 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index cb5c82a002d..07fe1983ef2 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -276,6 +276,7 @@ #define GEN8_SURFACE_TILING_W (1 << 12) #define GEN8_SURFACE_TILING_X (2 << 12) #define GEN8_SURFACE_TILING_Y (3 << 12) +#define GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE (1 << 9) #define BRW_SURFACE_RC_READ_WRITE (1 << 8) #define BRW_SURFACE_MIPLAYOUT_SHIFT 10 #define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index 6c4d3e197a5..d2f333fd4dd 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -238,6 +238,20 @@ gen8_emit_texture_surface_state(struct brw_context *brw, surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES; } + /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0 + * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes): + * + * This bit must be set for the following surface types: BC2_UNORM + * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM + */ + if ((brw->gen >= 9 || brw->is_cherryview) && + (format == BRW_SURFACEFORMAT_BC2_UNORM || + format == BRW_SURFACEFORMAT_BC3_UNORM || + format == BRW_SURFACEFORMAT_BC5_UNORM || + format == BRW_SURFACEFORMAT_BC5_SNORM || + format == BRW_SURFACEFORMAT_BC7_UNORM)) + surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE; + if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP) surf[0] |= GEN8_SURFACE_IS_ARRAY; |