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authorEric Anholt <[email protected]>2010-10-26 14:49:38 -0700
committerEric Anholt <[email protected]>2010-10-26 15:07:25 -0700
commitbb4f12f53875707a0d3c1eb254745b6250c42951 (patch)
tree86f8c806327512530745051fd5113347361d1f59 /src
parent00bfdac5b8e20463c04b9ec3f67bf1392fb86205 (diff)
i965: Disable register spilling on gen6 until it's fixed.
Avoids GPU hang on glsl-fs-convolution-1.
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index d7acc30fc46..bbb210cd449 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -225,7 +225,7 @@ fs_visitor::assign_regs()
* loop back into here to try again.
*/
int reg = choose_spill_reg(g);
- if (reg == -1) {
+ if (reg == -1 || intel->gen >= 6) {
this->fail = true;
} else {
spill_reg(reg);