diff options
| author | Samuel Pitoiset <[email protected]> | 2017-10-06 09:53:21 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2017-10-09 10:06:19 +0200 |
| commit | 7824cb4b03d972dc12d2ec249fad8fee6a2e137e (patch) | |
| tree | 01e47f78e8856c10c647d39932b0a56cf3b0ae5e /src | |
| parent | b09b43b166b1e532bdfb4960a33f9f82e7070029 (diff) | |
radv: configure VGT_VERTEX_REUSE at pipeline creation
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 18 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 7 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 1 |
3 files changed, 16 insertions, 10 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index a9e0fa51767..6a0640e2776 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -923,19 +923,17 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, } } -static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer, - struct radv_pipeline *pipeline) +static void +radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer, + struct radv_pipeline *pipeline) { - uint32_t vtx_reuse_depth = 30; + struct radeon_winsys_cs *cs = cmd_buffer->cs; + if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10) return; - if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) { - if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) - vtx_reuse_depth = 14; - } - radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, - vtx_reuse_depth); + radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, + pipeline->graphics.vtx_reuse_depth); } static void @@ -954,7 +952,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) radv_emit_tess_shaders(cmd_buffer, pipeline); radv_emit_geometry_shader(cmd_buffer, pipeline); radv_emit_fragment_shader(cmd_buffer, pipeline); - polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline); + radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline); cmd_buffer->scratch_size_needed = MAX2(cmd_buffer->scratch_size_needed, diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index c3458fa0372..7266fe02d67 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2087,6 +2087,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline, else pipeline->graphics.vtx_emit_num = 2; } + + pipeline->graphics.vtx_reuse_depth = 30; + if (radv_pipeline_has_tess(pipeline) && + pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) { + pipeline->graphics.vtx_reuse_depth = 14; + } + if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) { radv_dump_pipeline_stats(device, pipeline); } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index e4efd97d23e..4d2b2c696bf 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1095,6 +1095,7 @@ struct radv_pipeline { bool ia_switch_on_eoi; bool partial_vs_wave; uint8_t vtx_emit_num; + uint32_t vtx_reuse_depth; struct radv_prim_vertex_count prim_vertex_count; bool can_use_guardband; } graphics; |