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authorNicolai Hähnle <[email protected]>2017-07-04 11:09:50 +0200
committerNicolai Hähnle <[email protected]>2017-07-31 14:55:44 +0200
commit3997b10f74aec530eea4a3f64d179a8949c549e6 (patch)
treeed3ab881c728c4bba9929693af7db1fa262f3575 /src
parentb7d36efc2d38fa39e860a734a2265b35c2a34e9c (diff)
radeonsi/nir: lower uniforms to UBO loads
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeonsi/si_shader_nir.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 31da3a560fd..fce759b003d 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -32,6 +32,12 @@
#include "compiler/nir_types.h"
+static int
+type_size(const struct glsl_type *type)
+{
+ return glsl_count_attribute_slots(type, false);
+}
+
static void scan_instruction(struct tgsi_shader_info *info,
nir_instr *instr)
{
@@ -345,6 +351,10 @@ si_lower_nir(struct si_shader_selector* sel)
* - ensure constant offsets for texture instructions are folded
* and copy-propagated
*/
+ NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
+ (nir_lower_io_options)0);
+ NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
+
NIR_PASS_V(sel->nir, nir_lower_returns);
NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);