diff options
| author | Paul Berry <[email protected]> | 2011-08-23 11:43:46 -0700 |
|---|---|---|
| committer | Paul Berry <[email protected]> | 2011-09-06 11:04:26 -0700 |
| commit | f3ecc90730c1637b82e7a8eb8bef6d9a7a0531e8 (patch) | |
| tree | fd3cedbc924a929b63638fddec8e98f24154fe81 /src | |
| parent | ee3195a5ff9ce3e549fd254ecd751319a0bd9db5 (diff) | |
i965: new VS: Compute urb entry size based on the VUE map.
Previously, the new VS backend computed the size of the URB entry by
counting the number of MRFs used in emitting the URB entry. Now it
just gets it straight from the VUE map.
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 9738ee368b6..1b251fd7c19 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -1891,7 +1891,6 @@ vec4_visitor::emit_urb_writes() */ int base_mrf = 1; int mrf = base_mrf; - int urb_entry_size; /* In the process of generating our URB write message contents, we * may need to unspill a register or load from an array. Those * reads would use MRFs 14-15. @@ -1937,8 +1936,6 @@ vec4_visitor::emit_urb_writes() inst->mlen = align_interleaved_urb_mlen(brw, mrf - base_mrf); inst->eot = (slot >= c->vue_map.num_slots); - urb_entry_size = mrf - base_mrf; - /* Optional second URB write */ if (!inst->eot) { mrf = base_mrf + 1; @@ -1959,14 +1956,12 @@ vec4_visitor::emit_urb_writes() * those, since we're doing interleaved writes. */ inst->offset = (max_usable_mrf - base_mrf) / 2; - - urb_entry_size += mrf - base_mrf; } if (intel->gen == 6) - c->prog_data.urb_entry_size = ALIGN(urb_entry_size, 8) / 8; + c->prog_data.urb_entry_size = ALIGN(c->vue_map.num_slots, 8) / 8; else - c->prog_data.urb_entry_size = ALIGN(urb_entry_size, 4) / 4; + c->prog_data.urb_entry_size = ALIGN(c->vue_map.num_slots, 4) / 4; } src_reg |