radv: use ac_surface data structures

This is mostly mechanical changes of renaming types and introducing
"legacy" everywhere.

It doesn't use the ac_surface computation functions yet.

Reviewed-by: Dave Airlie <[email protected]>

8 files changed, 81 insertions, 153 deletions

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index db01e741e9b..582a67193f8 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -62,6 +62,7 @@ enum radeon_micro_mode {
 #define RADEON_SURF_SBUFFER                     (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
+#define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 88aaae738e5..1484003639e 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2643,9 +2643,9 @@ static inline unsigned
 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
 {
 	if (stencil)
-		return image->surface.stencil_tiling_index[level];
+		return image->surface.u.legacy.stencil_tiling_index[level];
 	else
-		return image->surface.tiling_index[level];
+		return image->surface.u.legacy.tiling_index[level];
 }
 
 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
@@ -2664,7 +2664,7 @@ radv_initialise_color_surface(struct radv_device *device,
 	unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
 	uint64_t va;
 	const struct radeon_surf *surf = &iview->image->surface;
-	const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
+	const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
 
 	desc = vk_format_description(iview->vk_format);
 
@@ -2792,7 +2792,7 @@ radv_initialise_color_surface(struct radv_device *device,
 	/* This must be set for fast clear to work without FMASK. */
 	if (!iview->image->fmask.size &&
 	    device->physical_device->rad_info.chip_class == SI) {
-		unsigned bankh = util_logbase2(iview->image->surface.bankh);
+		unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
 		cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
 	}
 }
@@ -2805,7 +2805,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 	unsigned level = iview->base_mip;
 	unsigned format;
 	uint64_t va, s_offs, z_offs;
-	const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
+	const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
 	bool stencil_only = false;
 	memset(ds, 0, sizeof(*ds));
 	switch (iview->vk_format) {
@@ -2827,7 +2827,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 		break;
 	case VK_FORMAT_S8_UINT:
 		stencil_only = true;
-		level_info = &iview->image->surface.stencil_level[level];
+		level_info = &iview->image->surface.u.legacy.stencil_level[level];
 		break;
 	default:
 		break;
@@ -2837,8 +2837,8 @@ radv_initialise_ds_surface(struct radv_device *device,
 
 	va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
 	s_offs = z_offs = va;
-	z_offs += iview->image->surface.level[level].offset;
-	s_offs += iview->image->surface.stencil_level[level].offset;
+	z_offs += iview->image->surface.u.legacy.level[level].offset;
+	s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
 
 	uint32_t max_slice = radv_surface_layer_count(iview);
 	ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
@@ -2856,9 +2856,9 @@ radv_initialise_ds_surface(struct radv_device *device,
 
 	if (device->physical_device->rad_info.chip_class >= CIK) {
 		struct radeon_info *info = &device->physical_device->rad_info;
-		unsigned tiling_index = iview->image->surface.tiling_index[level];
-		unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
-		unsigned macro_index = iview->image->surface.macro_tile_index;
+		unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
+		unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
+		unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
 		unsigned tile_mode = info->si_tile_mode_array[tiling_index];
 		unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
 		unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index e49a05383f7..63cbc6bf924 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -129,9 +129,9 @@ static inline unsigned
 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
 {
 	if (stencil)
-		return image->surface.stencil_tiling_index[level];
+		return image->surface.u.legacy.stencil_tiling_index[level];
 	else
-		return image->surface.tiling_index[level];
+		return image->surface.u.legacy.tiling_index[level];
 }
 
 static unsigned radv_map_swizzle(unsigned swizzle)
@@ -189,7 +189,7 @@ radv_make_buffer_descriptor(struct radv_device *device,
 static void
 si_set_mutable_tex_desc_fields(struct radv_device *device,
 			       struct radv_image *image,
-			       const struct radeon_surf_level *base_level_info,
+			       const struct legacy_surf_level *base_level_info,
 			       unsigned base_level, unsigned first_level,
 			       unsigned block_width, bool is_stencil,
 			       uint32_t *state)
@@ -409,7 +409,7 @@ radv_query_opaque_metadata(struct radv_device *device,
 				   image->info.depth,
 				   desc, NULL);
 
-	si_set_mutable_tex_desc_fields(device, image, &image->surface.level[0], 0, 0,
+	si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
 				       image->surface.blk_w, false, desc);
 
 	/* Clear the base address and set the relative DCC offset. */
@@ -422,7 +422,7 @@ radv_query_opaque_metadata(struct radv_device *device,
 
 	/* Dwords [10:..] contain the mipmap level offsets. */
 	for (i = 0; i <= image->info.levels - 1; i++)
-		md->metadata[10+i] = image->surface.level[i].offset >> 8;
+		md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
 
 	md->size_metadata = (11 + image->info.levels - 1) * 4;
 }
@@ -435,17 +435,17 @@ radv_init_metadata(struct radv_device *device,
 	struct radeon_surf *surface = &image->surface;
 
 	memset(metadata, 0, sizeof(*metadata));
-	metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
+	metadata->microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
 		RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
-	metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
+	metadata->macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
 		RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
-	metadata->pipe_config = surface->pipe_config;
-	metadata->bankw = surface->bankw;
-	metadata->bankh = surface->bankh;
-	metadata->tile_split = surface->tile_split;
-	metadata->mtilea = surface->mtilea;
-	metadata->num_banks = surface->num_banks;
-	metadata->stride = surface->level[0].nblk_x * surface->bpe;
+	metadata->pipe_config = surface->u.legacy.pipe_config;
+	metadata->bankw = surface->u.legacy.bankw;
+	metadata->bankh = surface->u.legacy.bankh;
+	metadata->tile_split = surface->u.legacy.tile_split;
+	metadata->mtilea = surface->u.legacy.mtilea;
+	metadata->num_banks = surface->u.legacy.num_banks;
+	metadata->stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
 	metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
 
 	radv_query_opaque_metadata(device, image, metadata);
@@ -460,7 +460,7 @@ radv_image_get_fmask_info(struct radv_device *device,
 {
 	/* FMASK is allocated like an ordinary texture. */
 	struct radeon_surf fmask = image->surface;
-	struct radeon_surf_info info = image->info;
+	struct ac_surf_info info = image->info;
 	memset(out, 0, sizeof(*out));
 
 	fmask.surf_alignment = 0;
@@ -488,15 +488,15 @@ radv_image_get_fmask_info(struct radv_device *device,
 	}
 
 	device->ws->surface_init(device->ws, &info, &fmask);
-	assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
+	assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
 
-	out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
+	out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
 	if (out->slice_tile_max)
 		out->slice_tile_max -= 1;
 
-	out->tile_mode_index = fmask.tiling_index[0];
-	out->pitch_in_pixels = fmask.level[0].nblk_x;
-	out->bank_height = fmask.bankh;
+	out->tile_mode_index = fmask.u.legacy.tiling_index[0];
+	out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
+	out->bank_height = fmask.u.legacy.bankh;
 	out->alignment = MAX2(256, fmask.surf_alignment);
 	out->size = fmask.surf_size;
 }
@@ -760,7 +760,9 @@ radv_image_view_init(struct radv_image_view *iview,
 				   iview->descriptor,
 				   iview->fmask_descriptor);
 	si_set_mutable_tex_desc_fields(device, image,
-				       is_stencil ? &image->surface.stencil_level[range->baseMipLevel] : &image->surface.level[range->baseMipLevel], range->baseMipLevel,
+				       is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
+				                  : &image->surface.u.legacy.level[range->baseMipLevel],
+				       range->baseMipLevel,
 				       range->baseMipLevel,
 				       blk_w, is_stencil, iview->descriptor);
 }
@@ -847,11 +849,11 @@ void radv_GetImageSubresourceLayout(
 	int layer = pSubresource->arrayLayer;
 	struct radeon_surf *surface = &image->surface;
 
-	pLayout->offset = surface->level[level].offset + surface->level[level].slice_size * layer;
-	pLayout->rowPitch = surface->level[level].nblk_x * surface->bpe;
-	pLayout->arrayPitch = surface->level[level].slice_size;
-	pLayout->depthPitch = surface->level[level].slice_size;
-	pLayout->size = surface->level[level].slice_size;
+	pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
+	pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
+	pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
+	pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
+	pLayout->size = surface->u.legacy.level[level].slice_size;
 	if (image->type == VK_IMAGE_TYPE_3D)
 		pLayout->size *= u_minify(image->info.depth, level);
 }
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 121a3ec52ee..66b77f406dc 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -900,7 +900,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
 	if (iview->image->info.levels > 1)
 		goto fail;
 
-	if (iview->image->surface.level[0].mode < RADEON_SURF_MODE_1D)
+	if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
 		goto fail;
 	if (!radv_image_extent_compare(iview->image, &iview->extent))
 		goto fail;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index c442f03ef89..bcb6783f536 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -53,6 +53,7 @@
 #include "radv_radeon_winsys.h"
 #include "ac_binary.h"
 #include "ac_nir_to_llvm.h"
+#include "ac_surface.h"
 #include "radv_debug.h"
 #include "radv_descriptor_set.h"
 
@@ -1176,7 +1177,7 @@ struct radv_image {
 	 */
 	VkFormat vk_format;
 	VkImageAspectFlags aspects;
-	struct radeon_surf_info info;
+	struct ac_surf_info info;
 	VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
 	VkImageTiling tiling; /** VkImageCreateInfo::tiling */
 	VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index 1d68629a247..817371497ed 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -35,6 +35,9 @@
 #include "main/macros.h"
 #include "amd_family.h"
 
+struct ac_surf_info;
+struct radeon_surf;
+
 #define FREE(x) free(x)
 
 enum radeon_bo_domain { /* bitfield */
@@ -126,8 +129,6 @@ struct radeon_info {
 	uint32_t                    cik_macrotile_mode_array[16];
 };
 
-#define RADEON_SURF_MAX_LEVEL                   32
-
 #define RADEON_SURF_TYPE_MASK                   0xFF
 #define RADEON_SURF_TYPE_SHIFT                  0
 #define     RADEON_SURF_TYPE_1D                     0
@@ -138,91 +139,11 @@ struct radeon_info {
 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 #define RADEON_SURF_MODE_MASK                   0xFF
 #define RADEON_SURF_MODE_SHIFT                  8
-#define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
-#define     RADEON_SURF_MODE_1D                     2
-#define     RADEON_SURF_MODE_2D                     3
-#define RADEON_SURF_SCANOUT                     (1 << 16)
-#define RADEON_SURF_ZBUFFER                     (1 << 17)
-#define RADEON_SURF_SBUFFER                     (1 << 18)
-#define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
-#define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
-#define RADEON_SURF_FMASK                       (1 << 21)
-#define RADEON_SURF_DISABLE_DCC                 (1 << 22)
-#define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 
 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 
-struct radeon_surf_info {
-	uint32_t width;
-	uint32_t height;
-	uint32_t depth;
-	uint8_t samples;
-	uint8_t levels;
-	uint16_t array_size;
-};
-
-struct radeon_surf_level {
-	uint64_t                    offset;
-	uint64_t                    slice_size;
-	uint32_t                    nblk_x;
-	uint32_t                    nblk_y;
-	uint32_t                    mode;
-	uint64_t                    dcc_offset;
-	uint64_t                    dcc_fast_clear_size;
-};
-
-
-/* surface defintions from the winsys */
-struct radeon_surf {
-	/* These are inputs to the calculator. */
-	uint32_t                    blk_w;
-	uint32_t                    blk_h;
-	uint32_t                    bpe;
-	uint32_t                    flags;
-
-	unsigned                    num_dcc_levels:4;
-
-	/* These are return values. Some of them can be set by the caller, but
-	 * they will be treated as hints (e.g. bankw, bankh) and might be
-	 * changed by the calculator.
-	 */
-	/* This applies to EG and later. */
-	uint32_t                    bankw;
-	uint32_t                    bankh;
-	uint32_t                    mtilea;
-	uint32_t                    tile_split;
-	uint32_t                    stencil_tile_split;
-	uint64_t                    stencil_offset;
-	struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
-	struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
-	uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
-	uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
-	uint32_t                    pipe_config;
-	uint32_t                    num_banks;
-	uint32_t                    macro_tile_index;
-	uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
-
-	/* Whether the depth miptree or stencil miptree as used by the DB are
-	 * adjusted from their TC compatible form to ensure depth/stencil
-	 * compatibility. If either is true, the corresponding plane cannot be
-	 * sampled from.
-	 */
-	bool                        depth_adjusted;
-	bool                        stencil_adjusted;
-
-	uint64_t                    surf_size;
-	uint64_t                    surf_alignment;
-
-	uint64_t                    dcc_size;
-	uint64_t                    dcc_alignment;
-
-	uint64_t                    htile_size;
-	uint64_t                    htile_slice_size;
-	uint64_t                    htile_alignment;
-};
-
 enum radeon_bo_layout {
 	RADEON_LAYOUT_LINEAR = 0,
 	RADEON_LAYOUT_TILED,
@@ -332,7 +253,7 @@ struct radeon_winsys {
 	void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id);
 
 	int (*surface_init)(struct radeon_winsys *ws,
-			    const struct radeon_surf_info *surf_info,
+			    const struct ac_surf_info *surf_info,
 			    struct radeon_surf *surf);
 
 	int (*surface_best)(struct radeon_winsys *ws,
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index d0ba37761ab..51fe159aaf8 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -224,7 +224,7 @@ radv_wsi_image_create(VkDevice device_h,
 	*memory_p = memory_h;
 	*size = image->size;
 	*offset = image->offset;
-	*row_pitch = surface->level[0].nblk_x * surface->bpe;
+	*row_pitch = surface->u.legacy.level[0].nblk_x * surface->bpe;
 	return VK_SUCCESS;
  fail_alloc_memory:
 	radv_FreeMemory(device_h, memory_h, pAllocator);
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index eb9c11c44ae..3a682c674c6 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -35,6 +35,8 @@
 #include "radv_amdgpu_surface.h"
 #include "sid.h"
 
+#include "ac_surface.h"
+
 #ifndef NO_ENTRIES
 #define NO_ENTRIES 32
 #endif
@@ -47,7 +49,7 @@
 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
 #endif
 
-static int radv_amdgpu_surface_sanity(const struct radeon_surf_info *surf_info,
+static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info,
 				      const struct radeon_surf *surf)
 {
 	unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
@@ -159,7 +161,7 @@ ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family,
 }
 
 static int radv_compute_level(ADDR_HANDLE addrlib,
-			      const struct radeon_surf_info *surf_info,
+			      const struct ac_surf_info *surf_info,
                               struct radeon_surf *surf, bool is_stencil,
                               unsigned level, unsigned type, bool compressed,
                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
@@ -167,7 +169,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
 {
-	struct radeon_surf_level *surf_level;
+	struct legacy_surf_level *surf_level;
 	ADDR_E_RETURNCODE ret;
 
 	AddrSurfInfoIn->mipLevel = level;
@@ -185,9 +187,9 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
 		/* Set the base level pitch. This is needed for calculation
 		 * of non-zero levels. */
 		if (is_stencil)
-			AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
+			AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
 		else
-			AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
+			AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
 
 		/* Convert blocks to pixels for compressed formats. */
 		if (compressed)
@@ -200,7 +202,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
 	if (ret != ADDR_OK)
 		return ret;
 
-	surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
+	surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
 	surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 	surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 	surf_level->nblk_x = AddrSurfInfoOut->pitch;
@@ -221,9 +223,9 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
 	}
 
 	if (is_stencil)
-		surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
+		surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 	else
-		surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
+		surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
 
 	surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 
@@ -282,7 +284,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
 static void radv_set_micro_tile_mode(struct radeon_surf *surf,
                                      struct radeon_info *info)
 {
-	uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
+	uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 
 	if (info->chip_class >= CIK)
 		surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
@@ -295,7 +297,7 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 	unsigned index, tileb;
 
 	tileb = 8 * 8 * surf->bpe;
-	tileb = MIN2(surf->tile_split, tileb);
+	tileb = MIN2(surf->u.legacy.tile_split, tileb);
 
 	for (index = 0; tileb > 64; index++)
 		tileb >>= 1;
@@ -305,7 +307,7 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 }
 
 static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
-					   const struct radeon_surf_info *surf_info,
+					   const struct ac_surf_info *surf_info,
 					   struct radeon_surf *surf)
 {
 	struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
@@ -422,15 +424,16 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 	/* Set preferred macrotile parameters. This is usually required
 	 * for shared resources. This is for 2D tiling only. */
 	if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
-	    surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
+	    surf->u.legacy.bankw && surf->u.legacy.bankh && surf->u.legacy.mtilea &&
+	    surf->u.legacy.tile_split) {
 		/* If any of these parameters are incorrect, the calculation
 		 * will fail. */
-		AddrTileInfoIn.banks = surf->num_banks;
-		AddrTileInfoIn.bankWidth = surf->bankw;
-		AddrTileInfoIn.bankHeight = surf->bankh;
-		AddrTileInfoIn.macroAspectRatio = surf->mtilea;
-		AddrTileInfoIn.tileSplitBytes = surf->tile_split;
-		AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
+		AddrTileInfoIn.banks = surf->u.legacy.num_banks;
+		AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
+		AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
+		AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
+		AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
+		AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 		AddrSurfInfoIn.flags.opt4Space = 0;
 		AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 
@@ -486,19 +489,19 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 
 		if (level == 0) {
 			surf->surf_alignment = AddrSurfInfoOut.baseAlign;
-			surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
+			surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 			radv_set_micro_tile_mode(surf, &ws->info);
 
 			/* For 2D modes only. */
 			if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
-				surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
-				surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
-				surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
-				surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
-				surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
-				surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
+				surf->u.legacy.bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
+				surf->u.legacy.bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
+				surf->u.legacy.mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
+				surf->u.legacy.tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
+				surf->u.legacy.num_banks = AddrSurfInfoOut.pTileInfo->banks;
+				surf->u.legacy.macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 			} else {
-				surf->macro_tile_index = 0;
+				surf->u.legacy.macro_tile_index = 0;
 			}
 		}
 	}
@@ -509,7 +512,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 		AddrSurfInfoIn.flags.depth = 0;
 		AddrSurfInfoIn.flags.stencil = 1;
 		/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
-		AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
+		AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
 
 		for (level = 0; level <= last_level; level++) {
 			r = radv_compute_level(ws->addrlib, surf_info, surf, true, level, type, compressed,
@@ -518,13 +521,13 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 				return r;
 
 			/* DB uses the depth pitch for both stencil and depth. */
-			if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
-				surf->stencil_adjusted = true;
+			if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
+				surf->u.legacy.stencil_adjusted = true;
 
 			if (level == 0) {
 				/* For 2D modes only. */
 				if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
-					surf->stencil_tile_split =
+					surf->u.legacy.stencil_tile_split =
 						AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 				}
 			}