diff options
| author | Topi Pohjolainen <[email protected]> | 2017-01-10 11:02:08 +0200 |
|---|---|---|
| committer | Topi Pohjolainen <[email protected]> | 2017-01-27 08:57:26 +0200 |
| commit | b864e3d7eee82accf3430b46d5a9269323fe0ba0 (patch) | |
| tree | e0c18c1f9e0fbf58805665301c0a723fe0583be7 /src | |
| parent | 40bf622cedda2fba54488188c98591354f16a132 (diff) | |
i965/gen6: Simplify hiz surface setup
In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo
is unconditionally initialised to point to the same buffer
object as hiz_mt does. The same goes for
intel_miptree_aux_buffer::pitch/qpitch.
This will make following patches simpler to read.
Reviewed-by: Jason Ekstrand <[email protected]>
Signed-off-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 5 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_depth_state.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 |
3 files changed, 6 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 616c0dff862..af050a0ace6 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -631,11 +631,10 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, /* Emit hiz buffer. */ if (hiz) { assert(depth_mt); - struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt; BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(hiz_mt->pitch - 1); - OUT_RELOC(hiz_mt->bo, + OUT_BATCH(depth_mt->hiz_buf->aux_base.pitch - 1); + OUT_RELOC(depth_mt->hiz_buf->aux_base.bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, brw->depthstencil.hiz_offset); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c index cb0ed253f9c..0ff240753e3 100644 --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c @@ -173,8 +173,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(hiz_mt->pitch - 1); - OUT_RELOC(hiz_mt->bo, + OUT_BATCH(depth_mt->hiz_buf->aux_base.pitch - 1); + OUT_RELOC(depth_mt->hiz_buf->aux_base.bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 19f4f883d7e..53dac330ef6 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -3442,13 +3442,8 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw, unreachable("Invalid MCS miptree"); } } else if (mt->hiz_buf) { - if (mt->hiz_buf->mt) { - aux_pitch = mt->hiz_buf->mt->pitch; - aux_qpitch = mt->hiz_buf->mt->qpitch; - } else { - aux_pitch = mt->hiz_buf->aux_base.pitch; - aux_qpitch = mt->hiz_buf->aux_base.qpitch; - } + aux_pitch = mt->hiz_buf->aux_base.pitch; + aux_qpitch = mt->hiz_buf->aux_base.qpitch; *usage = ISL_AUX_USAGE_HIZ; } else { |