diff options
| author | Kenneth Graunke <[email protected]> | 2014-09-26 15:50:14 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-10-01 01:05:36 -0700 |
| commit | a114f452aee29db752f895edff2b1062518c30a3 (patch) | |
| tree | cd68297b62bb219c0f28b618c2e3194221577af7 /src | |
| parent | 5105f9a7ae66001537e8dbf6acf40faf736430e5 (diff) | |
i965: Use ~0ull when flagging all BRW_NEW_* dirty flags.
~0 is 0xFFFFFFFF, which only covers the first 32 bits. We need all 64.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Chris Forbes <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_cache.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 2c00bce1351..20ce7b7c202 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -276,7 +276,7 @@ retry: /* We've smashed all state compared to what the normal 3D pipeline * rendering tracks for GL. */ - brw->state.dirty.brw = ~0; + brw->state.dirty.brw = ~0ull; brw->state.dirty.cache = ~0; brw->no_depth_or_stencil = false; brw->ib.type = -1; diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index 882d131a62c..62e03b12984 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -379,7 +379,7 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache) * any offsets leftover in brw_context will no longer be valid. */ brw->state.dirty.mesa |= ~0; - brw->state.dirty.brw |= ~0; + brw->state.dirty.brw |= ~0ull; brw->state.dirty.cache |= ~0; intel_batchbuffer_flush(brw); } diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index e124ce4485d..9e3cfb800e3 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -388,7 +388,7 @@ void brw_init_state( struct brw_context *brw ) brw_upload_initial_gpu_state(brw); brw->state.dirty.mesa = ~0; - brw->state.dirty.brw = ~0; + brw->state.dirty.brw = ~0ull; /* Make sure that brw->state.dirty.brw has enough bits to hold all possible * dirty flags. @@ -575,7 +575,7 @@ void brw_upload_state(struct brw_context *brw) if (0) { /* Always re-emit all state. */ state->mesa |= ~0; - state->brw |= ~0; + state->brw |= ~0ull; state->cache |= ~0; } |