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authorJordan Justen <[email protected]>2013-07-09 15:32:42 -0700
committerJordan Justen <[email protected]>2014-08-15 20:11:41 -0700
commit96306a6cbb51bb7f637dcd684c22003c64171c82 (patch)
treea90057d0d25331a89ebf54bb56aa710691a4bdb0 /src
parent039eb81abf4fab94e787ddd4d5ca4133f7af9c1c (diff)
i965/gen6 blorp depth: calculate base surface width/height
(e3a49e1 for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 23e3aa266e5..b422dc995c6 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -780,6 +780,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t draw_x = params->depth.x_offset;
uint32_t draw_y = params->depth.y_offset;
uint32_t tile_mask_x, tile_mask_y;
+ uint32_t surfwidth, surfheight;
uint32_t surftype;
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
GLenum gl_target = params->depth.mt->target;
@@ -811,6 +812,18 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
lod = params->depth.level - params->depth.mt->first_level;
+ if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
+ /* HIZ ops for lod 0 may set the width & height a little
+ * larger to allow the fast depth clear to fit the hardware
+ * alignment requirements. (8x4)
+ */
+ surfwidth = params->depth.width;
+ surfheight = params->depth.height;
+ } else {
+ surfwidth = params->depth.mt->logical_width0;
+ surfheight = params->depth.mt->logical_height0;
+ }
+
/* 3DSTATE_DEPTH_BUFFER */
{
uint32_t tile_x = draw_x & tile_mask_x;