r600g: Deobfuscate and comment a few more functions in r600_hw_states.

2 files changed, 66 insertions, 11 deletions

diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c
index 17851a9b6e8..5ad396dc152 100644
--- a/src/gallium/drivers/r600/r600_hw_states.c
+++ b/src/gallium/drivers/r600/r600_hw_states.c
@@ -197,7 +197,7 @@ static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rsta
 	float offset_units = 0, offset_scale = 0;
 	char depth = 0;
 	unsigned offset_db_fmt_cntl = 0;
-	unsigned tmp;
+	unsigned point_size;
 	unsigned prov_vtx = 1;
 
 	if (rctx->clip)
@@ -248,9 +248,18 @@ static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rsta
 	}
 	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
 	if (clip) {
-		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
-		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
-		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
+		/* Clip plane enable bits are stashed in the lower six bits of
+		 * PA_CL_CLIP_CNTL, so just set all of the corresponding bits with a
+		 * pinch of bit twiddling.
+		 *
+		 * PS_UCP_MODE 3 is "expand and clip as trifan," which is the same
+		 * setting that we use on r300-r500. I believe that fglrx always uses
+		 * this mode as well. */
+		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] =
+			((1 << clip->nr) - 1) |
+			S_028810_PS_UCP_MODE(3) |
+			S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp) |
+			S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
 	}
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
 		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
@@ -264,14 +273,20 @@ static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rsta
 			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
 			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
 	rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
-	/* point size 12.4 fixed point */
-	tmp = (unsigned)(state->point_size * 8.0);
-	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
-	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
-	rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
+	/* Point size for PA_SU_POINT_SIZE and PA_SU_POINT_MINMAX is fixed-point,
+	 * 12.4.
+	 *
+	 * For some reason, maximum point size is set to 0x8000 (2048.0) instead
+	 * of the maximum value 0xFFF0 (4095.0). */
+	point_size = (unsigned)(state->point_size * 8.0);
+	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] =
+		S_028A00_HEIGHT(point_size) | S_028A00_WIDTH(point_size);
+	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] =
+		S_028A04_MIN_SIZE(0) | S_028A04_MAX_SIZE(0x8000);
+	rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = S_028A08_WIDTH(8);
 	rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
 	rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
+	rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = S_028C00_LAST_PIXEL(1);
 	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = fui(1);
 	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = fui(1);
 	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = fui(1);
@@ -349,7 +364,14 @@ static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
-	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
+	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] =
+		S_028818_VPORT_X_SCALE_ENA(1) |
+		S_028818_VPORT_X_OFFSET_ENA(1) |
+		S_028818_VPORT_Y_SCALE_ENA(1) |
+		S_028818_VPORT_Y_OFFSET_ENA(1) |
+		S_028818_VPORT_Z_SCALE_ENA(1) |
+		S_028818_VPORT_Z_OFFSET_ENA(1) |
+		S_028818_VTX_W0_FMT(1);
 	radeon_state_pm4(rstate);
 }
 
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 07bfc0593e9..3ca3cc764b6 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -2112,6 +2112,9 @@
 #define R_0286D4_SPI_INTERP_CONTROL_0                0x0286D4
 #define R_028A48_PA_SC_MPASS_PS_CNTL                 0x028A48
 #define R_028C00_PA_SC_LINE_CNTL                     0x028C00
+#define   S_028C00_LAST_PIXEL(x)                       (((x) & 0x1) << 10)
+#define   G_028C00_LAST_PIXEL(x)                       (((x) >> 10) & 0x1)
+#define   C_028C00_LAST_PIXEL                          0xFFFFFBFF
 #define R_028C04_PA_SC_AA_CONFIG                     0x028C04
 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x028C1C
 #define R_028C48_PA_SC_AA_MASK                       0x028C48
@@ -2125,7 +2128,16 @@
 #define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
 #define R_028A00_PA_SU_POINT_SIZE                    0x028A00
 #define R_028A04_PA_SU_POINT_MINMAX                  0x028A04
+#define   S_028A04_MIN_SIZE(x)                         (((x) & 0xFFFF) << 0)
+#define   G_028A04_MIN_SIZE(x)                         (((x) >> 0) & 0xFFFF)
+#define   C_028A04_MIN_SIZE                            0xFFFF0000
+#define   S_028A04_MAX_SIZE(x)                         (((x) & 0xFFFF) << 16)
+#define   G_028A04_MAX_SIZE(x)                         (((x) >> 16) & 0xFFFF)
+#define   C_028A04_MAX_SIZE                            0x0000FFFF
 #define R_028A08_PA_SU_LINE_CNTL                     0x028A08
+#define   S_028A08_WIDTH(x)                            (((x) & 0xFFFF) << 0)
+#define   G_028A08_WIDTH(x)                            (((x) >> 0) & 0xFFFF)
+#define   C_028A08_WIDTH                               0xFFFF0000
 #define R_028A0C_PA_SC_LINE_STIPPLE                  0x028A0C
 #define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
 #define R_028DFC_PA_SU_POLY_OFFSET_CLAMP             0x028DFC
@@ -2134,6 +2146,27 @@
 #define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
 #define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
 #define R_028818_PA_CL_VTE_CNTL                      0x028818
+#define   S_028818_VPORT_X_SCALE_ENA(x)                (((x) & 0x1) << 0)
+#define   G_028818_VPORT_X_SCALE_ENA(x)                (((x) >> 0 & 0x1)
+#define   C_028818_VPORT_X_SCALE_ENA                   0xFFFFFFFE
+#define   S_028818_VPORT_X_OFFSET_ENA(x)               (((x) & 0x1) << 1)
+#define   G_028818_VPORT_X_OFFSET_ENA(x)               (((x) >> 1 & 0x1)
+#define   C_028818_VPORT_X_OFFSET_ENA                  0xFFFFFFFD
+#define   S_028818_VPORT_Y_SCALE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_028818_VPORT_Y_SCALE_ENA(x)                (((x) >> 2 & 0x1)
+#define   C_028818_VPORT_Y_SCALE_ENA                   0xFFFFFFFB
+#define   S_028818_VPORT_Y_OFFSET_ENA(x)               (((x) & 0x1) << 3)
+#define   G_028818_VPORT_Y_OFFSET_ENA(x)               (((x) >> 3 & 0x1)
+#define   C_028818_VPORT_Y_OFFSET_ENA                  0xFFFFFFF7
+#define   S_028818_VPORT_Z_SCALE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_028818_VPORT_Z_SCALE_ENA(x)                (((x) >> 4 & 0x1)
+#define   C_028818_VPORT_Z_SCALE_ENA                   0xFFFFFFEF
+#define   S_028818_VPORT_Z_OFFSET_ENA(x)               (((x) & 0x1) << 5)
+#define   G_028818_VPORT_Z_OFFSET_ENA(x)               (((x) >> 5 & 0x1)
+#define   C_028818_VPORT_Z_OFFSET_ENA                  0xFFFFFFDF
+#define   S_028818_VTX_W0_FMT(x)                       (((x) & 0x1) << 10)
+#define   G_028818_VTX_W0_FMT(x)                       (((x) >> 10) & 0x1)
+#define   C_028818_VTX_W0_FMT                          0xFFFFFBFF
 #define R_02843C_PA_CL_VPORT_XSCALE_0                0x02843C
 #define R_028444_PA_CL_VPORT_YSCALE_0                0x028444
 #define R_02844C_PA_CL_VPORT_ZSCALE_0                0x02844C