diff options
| author | Marek Olšák <[email protected]> | 2015-10-22 11:10:14 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-10-27 10:49:24 +0100 |
| commit | 5bc5dca0cbcb1a13fbe9b3a33489e88531d1eb33 (patch) | |
| tree | 406983754390a81468c086625a8e8a9ed919e47c /src | |
| parent | 3daa7e5147f164e822269f13c3bcccfa6446fa83 (diff) | |
radeonsi: simplify DCC handling in si_initialize_color_surface
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 384c8e28faa..c87f661f278 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1926,8 +1926,9 @@ static void si_initialize_color_surface(struct si_context *sctx, surf->cb_color_info = color_info; surf->cb_color_attrib = color_attrib; - if (sctx->b.chip_class >= VI) { + if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) { unsigned max_uncompressed_block_size = 2; + uint64_t dcc_offset = rtex->surface.level[level].dcc_offset; if (rtex->surface.nsamples > 1) { if (rtex->surface.bpe == 1) @@ -1938,12 +1939,7 @@ static void si_initialize_color_surface(struct si_context *sctx, surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) | S_028C78_INDEPENDENT_64B_BLOCKS(1); - - if (rtex->surface.dcc_enabled) { - uint64_t dcc_offset = rtex->surface.level[level].dcc_offset; - - surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8; - } + surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8; } if (rtex->fmask.size) { |