diff options
| author | Marek Olšák <[email protected]> | 2015-08-10 16:23:53 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-08-14 15:02:31 +0200 |
| commit | f47c59322e614d6304091207fc81cfa5beba6ea9 (patch) | |
| tree | deb0216ed6f722adb656b66a93a0928d9878fa88 /src | |
| parent | 839bf82606ae9c7b1c7d8d5055ab5e3cadae9bf9 (diff) | |
radeonsi: revert a wrong DB bug workaround for VI
The bug was misunderstood. Besides that, the bug affects a DB feature we
don't use yet.
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 21689e71b8b..c923ea7e154 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1994,10 +1994,6 @@ static void si_init_depth_surface(struct si_context *sctx, db_htile_surface = 0; } - /* Bug workaround. */ - if (sctx->b.chip_class >= VI) - s_info |= S_028044_TILE_STENCIL_DISABLE(1); - assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) | |