radeonsi: move texture storage allocation outside of radeonsi

possible code sharing with radv

Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>

4 files changed, 97 insertions, 51 deletions

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 1d254ec3a78..4b0e4f70535 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1679,7 +1679,61 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 		return r;
 
 	if (info->chip_class >= GFX9)
-		return gfx9_compute_surface(addrlib, info, config, mode, surf);
+		r = gfx9_compute_surface(addrlib, info, config, mode, surf);
 	else
-		return gfx6_compute_surface(addrlib, info, config, mode, surf);
+		r = gfx6_compute_surface(addrlib, info, config, mode, surf);
+
+	if (r)
+		return r;
+
+	/* Determine the memory layout of multiple allocations in one buffer. */
+	surf->total_size = surf->surf_size;
+
+	if (surf->htile_size) {
+		surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
+		surf->total_size = surf->htile_offset + surf->htile_size;
+	}
+
+	if (surf->fmask_size) {
+		assert(config->info.samples >= 2);
+		surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
+		surf->total_size = surf->fmask_offset + surf->fmask_size;
+	}
+
+	/* Single-sample CMASK is in a separate buffer. */
+	if (surf->cmask_size && config->info.samples >= 2) {
+		surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
+		surf->total_size = surf->cmask_offset + surf->cmask_size;
+	}
+
+	if (surf->dcc_size &&
+	    (info->use_display_dcc_unaligned ||
+	     info->use_display_dcc_with_retile_blit ||
+	     !(surf->flags & RADEON_SURF_SCANOUT))) {
+		surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
+		surf->total_size = surf->dcc_offset + surf->dcc_size;
+
+		if (info->chip_class >= GFX9 &&
+		    surf->u.gfx9.dcc_retile_num_elements) {
+			/* Add space for the displayable DCC buffer. */
+			surf->display_dcc_offset =
+				align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
+			surf->total_size = surf->display_dcc_offset +
+					   surf->u.gfx9.display_dcc_size;
+
+			/* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
+			surf->dcc_retile_map_offset =
+				align64(surf->total_size, info->tcc_cache_line_size);
+
+			if (surf->u.gfx9.dcc_retile_use_uint16) {
+				surf->total_size = surf->dcc_retile_map_offset +
+						   surf->u.gfx9.dcc_retile_num_elements * 2;
+			} else {
+				surf->total_size = surf->dcc_retile_map_offset +
+						   surf->u.gfx9.dcc_retile_num_elements * 4;
+			}
+		}
+	}
+
+	return 0;
 }
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 52aa63bff2e..c838bd47da5 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -227,6 +227,15 @@ struct radeon_surf {
     uint32_t                    cmask_slice_size;
     uint32_t                    cmask_alignment;
 
+    /* All buffers combined. */
+    uint64_t                    htile_offset;
+    uint64_t                    fmask_offset;
+    uint64_t                    cmask_offset;
+    uint64_t                    dcc_offset;
+    uint64_t                    display_dcc_offset;
+    uint64_t                    dcc_retile_map_offset;
+    uint64_t                    total_size;
+
     union {
         /* Return values for GFX8 and older.
          *
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 439de3d0ffa..ddef8da4e14 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1243,10 +1243,7 @@ si_texture_create_object(struct pipe_screen *screen,
 
 	/* don't include stencil-only formats which we don't support for rendering */
 	tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format));
-
 	tex->surface = *surface;
-	tex->size = tex->surface.surf_size;
-
 	tex->tc_compatible_htile = tex->surface.htile_size != 0 &&
 				   (tex->surface.flags &
 				    RADEON_SURF_TC_COMPATIBLE_HTILE);
@@ -1276,6 +1273,15 @@ si_texture_create_object(struct pipe_screen *screen,
 	 */
 	tex->ps_draw_ratio = 0;
 
+	/* TODO: remove these */
+	tex->fmask_offset = tex->surface.fmask_offset;
+	tex->cmask_offset = tex->surface.cmask_offset;
+	tex->htile_offset = tex->surface.htile_offset;
+	tex->dcc_offset = tex->surface.dcc_offset;
+	tex->display_dcc_offset = tex->surface.display_dcc_offset;
+	tex->dcc_retile_map_offset = tex->surface.dcc_retile_map_offset;
+	tex->size = tex->surface.total_size;
+
 	if (tex->is_depth) {
 		if (sscreen->info.chip_class >= GFX9) {
 			tex->can_sample_z = true;
@@ -1294,55 +1300,11 @@ si_texture_create_object(struct pipe_screen *screen,
 		}
 
 		tex->db_compatible = surface->flags & RADEON_SURF_ZBUFFER;
-
-		if (tex->surface.htile_size) {
-			tex->htile_offset = align64(tex->size,
-						    tex->surface.htile_alignment);
-			tex->size = tex->htile_offset + tex->surface.htile_size;
-		}
 	} else {
-		if (tex->surface.fmask_size) {
-			/* Allocate FMASK. */
-			tex->fmask_offset = align64(tex->size,
-						     tex->surface.fmask_alignment);
-			tex->size = tex->fmask_offset + tex->surface.fmask_size;
-
-			/* Allocate CMASK. */
-			tex->cmask_offset = align64(tex->size, tex->surface.cmask_alignment);
-			tex->size = tex->cmask_offset + tex->surface.cmask_size;
+		if (tex->surface.cmask_offset) {
 			tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
 			tex->cmask_buffer = &tex->buffer;
 		}
-
-		if (tex->surface.dcc_size &&
-		    (sscreen->info.use_display_dcc_unaligned ||
-		     sscreen->info.use_display_dcc_with_retile_blit ||
-		     !(tex->surface.flags & RADEON_SURF_SCANOUT))) {
-			/* Add space for the DCC buffer. */
-			tex->dcc_offset = align64(tex->size, tex->surface.dcc_alignment);
-			tex->size = tex->dcc_offset + tex->surface.dcc_size;
-
-			if (sscreen->info.chip_class >= GFX9 &&
-			    tex->surface.u.gfx9.dcc_retile_num_elements) {
-				/* Add space for the displayable DCC buffer. */
-				tex->display_dcc_offset =
-					align64(tex->size, tex->surface.u.gfx9.display_dcc_alignment);
-				tex->size = tex->display_dcc_offset +
-					    tex->surface.u.gfx9.display_dcc_size;
-
-				/* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
-				tex->dcc_retile_map_offset =
-					align64(tex->size, sscreen->info.tcc_cache_line_size);
-
-				if (tex->surface.u.gfx9.dcc_retile_use_uint16) {
-					tex->size = tex->dcc_retile_map_offset +
-						    tex->surface.u.gfx9.dcc_retile_num_elements * 2;
-				} else {
-					tex->size = tex->dcc_retile_map_offset +
-						    tex->surface.u.gfx9.dcc_retile_num_elements * 4;
-				}
-			}
-		}
 	}
 
 	/* Now create the backing buffer. */
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 332b9e4a428..a49f3eb4ed8 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -432,9 +432,30 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
 	    si_compute_cmask(&ws->info, &config, surf_ws);
     }
 
-    if (ws->gen == DRV_SI)
+    if (ws->gen == DRV_SI) {
         si_compute_htile(&ws->info, surf_ws, util_num_layers(tex, 0));
 
+	/* Determine the memory layout of multiple allocations in one buffer. */
+	surf_ws->total_size = surf_ws->surf_size;
+
+	if (surf_ws->htile_size) {
+		surf_ws->htile_offset = align64(surf_ws->total_size, surf_ws->htile_alignment);
+		surf_ws->total_size = surf_ws->htile_offset + surf_ws->htile_size;
+	}
+
+	if (surf_ws->fmask_size) {
+		assert(tex->nr_samples >= 2);
+		surf_ws->fmask_offset = align64(surf_ws->total_size, surf_ws->fmask_alignment);
+		surf_ws->total_size = surf_ws->fmask_offset + surf_ws->fmask_size;
+	}
+
+	/* Single-sample CMASK is in a separate buffer. */
+	if (surf_ws->cmask_size && tex->nr_samples >= 2) {
+		surf_ws->cmask_offset = align64(surf_ws->total_size, surf_ws->cmask_alignment);
+		surf_ws->total_size = surf_ws->cmask_offset + surf_ws->cmask_size;
+	}
+    }
+
     return 0;
 }