diff options
| author | Jordan Justen <[email protected]> | 2019-05-25 01:33:17 -0700 |
|---|---|---|
| committer | Jordan Justen <[email protected]> | 2019-12-02 16:34:12 -0800 |
| commit | e277009d8dbdc9aec4be26aed5357ec41f359937 (patch) | |
| tree | a179e5656489cf98ff2f6299bf269bed97170fd5 /src | |
| parent | 7730d583c207002e14ca2e95d30cab181db20082 (diff) | |
iris: Allow max dynamic pool size of 2GB for gen12
Reworks:
* Adjust comment to list the state packets that curro found to be
affected.
Fixes: 8125d7960b6 ("intel/dev: Add preliminary device info for Tigerlake")
Cc: 19.3 <[email protected]>
Signed-off-by: Jordan Justen <[email protected]>
Acked-by: Kenneth Graunke <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/iris/iris_bufmgr.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c index 158cb41d383..167538d49c4 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.c +++ b/src/gallium/drivers/iris/iris_bufmgr.c @@ -1667,6 +1667,7 @@ iris_bufmgr_init(struct gen_device_info *devinfo, int fd, bool bo_reuse) STATIC_ASSERT(IRIS_MEMZONE_SHADER_START == 0ull); const uint64_t _4GB = 1ull << 32; + const uint64_t _2GB = 1ul << 31; /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */ const uint64_t _4GB_minus_1 = _4GB - PAGE_SIZE; @@ -1676,9 +1677,16 @@ iris_bufmgr_init(struct gen_device_info *devinfo, int fd, bool bo_reuse) util_vma_heap_init(&bufmgr->vma_allocator[IRIS_MEMZONE_SURFACE], IRIS_MEMZONE_SURFACE_START, _4GB_minus_1 - IRIS_MAX_BINDERS * IRIS_BINDER_SIZE); + /* TODO: Why does limiting to 2GB help some state items on gen12? + * - CC Viewport Pointer + * - Blend State Pointer + * - Color Calc State Pointer + */ + const uint64_t dynamic_pool_size = + (devinfo->gen >= 12 ? _2GB : _4GB_minus_1) - IRIS_BORDER_COLOR_POOL_SIZE; util_vma_heap_init(&bufmgr->vma_allocator[IRIS_MEMZONE_DYNAMIC], IRIS_MEMZONE_DYNAMIC_START + IRIS_BORDER_COLOR_POOL_SIZE, - _4GB_minus_1 - IRIS_BORDER_COLOR_POOL_SIZE); + dynamic_pool_size); /* Leave the last 4GB out of the high vma range, so that no state * base address + size can overflow 48 bits. |