diff options
author | Matt Turner <[email protected]> | 2016-10-17 14:10:26 -0700 |
---|---|---|
committer | Ian Romanick <[email protected]> | 2019-07-30 14:35:43 -0700 |
commit | dabb5d4bee0705deba29e96725b6f8a63943c28e (patch) | |
tree | 591fdc4ea3f0a8e324b633b836858bc4ea8091ee /src | |
parent | 11a49f289d17128c24dd9aa339b940b819cb7e41 (diff) |
i965/fs: Add a shader_stats struct.
It'll grow further, and we'd like to avoid adding an additional
parameter to fs_generator() for each new piece of data.
v2 (idr): Rebase on 17 months. Track a visitor instead of a cfg.
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src')
-rw-r--r-- | src/intel/compiler/brw_fs.cpp | 25 | ||||
-rw-r--r-- | src/intel/compiler/brw_fs.h | 11 | ||||
-rw-r--r-- | src/intel/compiler/brw_fs_combine_constants.cpp | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 8 | ||||
-rw-r--r-- | src/intel/compiler/brw_fs_visitor.cpp | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_shader.cpp | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_vec4_gs_visitor.cpp | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_vec4_tcs.cpp | 2 |
9 files changed, 29 insertions, 27 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index c8dae0c85d9..c5d30a0e7ed 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -8108,7 +8108,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, } fs_generator g(compiler, log_data, mem_ctx, &prog_data->base, - v8.promoted_constants, v8.runtime_check_aads_emit, + v8.shader_stats, v8.runtime_check_aads_emit, MESA_SHADER_FRAGMENT); if (unlikely(INTEL_DEBUG & DEBUG_WM)) { @@ -8258,9 +8258,8 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, unsigned max_dispatch_width = 32; fs_visitor *v8 = NULL, *v16 = NULL, *v32 = NULL; - cfg_t *cfg = NULL; + fs_visitor *v = NULL; const char *fail_msg = NULL; - unsigned promoted_constants = 0; if ((int)key->base.subgroup_size_type >= (int)BRW_SUBGROUP_SIZE_REQUIRE_8) { /* These enum values are expressly chosen to be equal to the subgroup @@ -8294,10 +8293,9 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, /* We should always be able to do SIMD32 for compute shaders */ assert(v8->max_dispatch_width >= 32); - cfg = v8->cfg; + v = v8; cs_set_simd_size(prog_data, 8); cs_fill_push_const_info(compiler->devinfo, prog_data); - promoted_constants = v8->promoted_constants; } } @@ -8317,7 +8315,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, compiler->shader_perf_log(log_data, "SIMD16 shader failed to compile: %s", v16->fail_msg); - if (!cfg) { + if (!v) { fail_msg = "Couldn't generate SIMD16 program and not " "enough threads for SIMD8"; @@ -8326,10 +8324,9 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, /* We should always be able to do SIMD32 for compute shaders */ assert(v16->max_dispatch_width >= 32); - cfg = v16->cfg; + v = v16; cs_set_simd_size(prog_data, 16); cs_fill_push_const_info(compiler->devinfo, prog_data); - promoted_constants = v16->promoted_constants; } } @@ -8354,27 +8351,27 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, compiler->shader_perf_log(log_data, "SIMD32 shader failed to compile: %s", v16->fail_msg); - if (!cfg) { + if (!v) { fail_msg = "Couldn't generate SIMD32 program and not " "enough threads for SIMD16"; } } else { - cfg = v32->cfg; + v = v32; cs_set_simd_size(prog_data, 32); cs_fill_push_const_info(compiler->devinfo, prog_data); - promoted_constants = v32->promoted_constants; } } const unsigned *ret = NULL; - if (unlikely(cfg == NULL)) { + if (unlikely(v == NULL)) { assert(fail_msg); if (error_str) *error_str = ralloc_strdup(mem_ctx, fail_msg); } else { fs_generator g(compiler, log_data, mem_ctx, &prog_data->base, - promoted_constants, false, MESA_SHADER_COMPUTE); + v->shader_stats, v->runtime_check_aads_emit, + MESA_SHADER_COMPUTE); if (INTEL_DEBUG & DEBUG_CS) { char *name = ralloc_asprintf(mem_ctx, "%s compute shader %s", src_shader->info.label ? @@ -8383,7 +8380,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, g.enable_debug(name); } - g.generate_code(cfg, prog_data->simd_size); + g.generate_code(v->cfg, prog_data->simd_size); ret = g.get_assembly(); } diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index e0e337d46c0..8aa3d3482c9 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -52,6 +52,10 @@ offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta) #define UBO_START ((1 << 16) - 4) +struct shader_stats { + unsigned promoted_constants; +}; + /** * The fragment shader front-end. * @@ -389,7 +393,8 @@ public: int shader_time_index; - unsigned promoted_constants; + struct shader_stats shader_stats; + brw::fs_builder bld; private: @@ -413,7 +418,7 @@ public: fs_generator(const struct brw_compiler *compiler, void *log_data, void *mem_ctx, struct brw_stage_prog_data *prog_data, - unsigned promoted_constants, + struct shader_stats shader_stats, bool runtime_check_aads_emit, gl_shader_stage stage); ~fs_generator(); @@ -517,7 +522,7 @@ private: unsigned dispatch_width; /**< 8, 16 or 32 */ exec_list discard_halt_patches; - unsigned promoted_constants; + struct shader_stats shader_stats; bool runtime_check_aads_emit; bool debug_flag; const char *shader_name; diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp b/src/intel/compiler/brw_fs_combine_constants.cpp index c12e0d62293..0fff87820e1 100644 --- a/src/intel/compiler/brw_fs_combine_constants.cpp +++ b/src/intel/compiler/brw_fs_combine_constants.cpp @@ -442,7 +442,7 @@ fs_visitor::opt_combine_constants() reg.offset += imm->size * width; } - promoted_constants = table.len; + shader_stats.promoted_constants = table.len; /* Rewrite the immediate sources to refer to the new GRFs. */ for (int i = 0; i < table.len; i++) { diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 88de5189064..d9abf9a0153 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -183,14 +183,14 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst, fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data, void *mem_ctx, struct brw_stage_prog_data *prog_data, - unsigned promoted_constants, + struct shader_stats shader_stats, bool runtime_check_aads_emit, gl_shader_stage stage) : compiler(compiler), log_data(log_data), devinfo(compiler->devinfo), prog_data(prog_data), - promoted_constants(promoted_constants), + shader_stats(shader_stats), runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false), stage(stage), mem_ctx(mem_ctx) { @@ -2253,7 +2253,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d" " bytes (%.0f%%)\n", shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count, - spill_count, fill_count, promoted_constants, before_size, after_size, + spill_count, fill_count, shader_stats.promoted_constants, before_size, after_size, 100.0f * (before_size - after_size) / before_size); dump_assembly(p->store, disasm_info); @@ -2268,7 +2268,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) _mesa_shader_stage_to_abbrev(stage), dispatch_width, before_size / 16, loop_count, cfg->cycle_count, spill_count, - fill_count, promoted_constants, before_size, + fill_count, shader_stats.promoted_constants, before_size, after_size); return start_offset; diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 869f8c9017b..72e94beaf17 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -952,7 +952,7 @@ fs_visitor::init() this->pull_constant_loc = NULL; this->push_constant_loc = NULL; - this->promoted_constants = 0, + this->shader_stats.promoted_constants = 0, this->grf_used = 0; this->spilled_any_registers = false; diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 5f86e251c33..630a51aaf3f 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1335,7 +1335,7 @@ brw_compile_tes(const struct brw_compiler *compiler, prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; fs_generator g(compiler, log_data, mem_ctx, - &prog_data->base.base, v.promoted_constants, false, + &prog_data->base.base, v.shader_stats, false, MESA_SHADER_TESS_EVAL); if (unlikely(INTEL_DEBUG & DEBUG_TES)) { g.enable_debug(ralloc_asprintf(mem_ctx, diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 2014f95f9c7..b4ad21cf776 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2975,7 +2975,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; fs_generator g(compiler, log_data, mem_ctx, - &prog_data->base.base, v.promoted_constants, + &prog_data->base.base, v.shader_stats, v.runtime_check_aads_emit, MESA_SHADER_VERTEX); if (INTEL_DEBUG & DEBUG_VS) { const char *debug_name = diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp index b7476afb466..aae0e1b4baf 100644 --- a/src/intel/compiler/brw_vec4_gs_visitor.cpp +++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp @@ -856,7 +856,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; fs_generator g(compiler, log_data, mem_ctx, - &prog_data->base.base, v.promoted_constants, + &prog_data->base.base, v.shader_stats, false, MESA_SHADER_GEOMETRY); if (unlikely(INTEL_DEBUG & DEBUG_GS)) { const char *label = diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index a107a9b6630..712766ca89a 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -487,7 +487,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; fs_generator g(compiler, log_data, mem_ctx, - &prog_data->base.base, v.promoted_constants, false, + &prog_data->base.base, v.shader_stats, false, MESA_SHADER_TESS_CTRL); if (unlikely(INTEL_DEBUG & DEBUG_TCS)) { g.enable_debug(ralloc_asprintf(mem_ctx, |