intel/isl: Implement D16_UNORM workarounds.

GEN:BUG:14010455700 (lineage 1808121037):

   "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
   Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"

Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501.

GEN:BUG:1806527549:

   "Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM."

This one could fix a GPU hang in some workloads.

v2: Implement WA in isl and add another similar WA (Jason).
v3: Add flushes before changing chicken registers (Jason)
v4: Depth flush and stall + end of pipe sync when changing registers
(Jason).

Reviewed-by: Jason Ekstrand <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>

5 files changed, 93 insertions, 4 deletions

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 3a2d7140c1e..5574b073a79 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1056,7 +1056,8 @@ struct iris_depth_buffer_state {
    uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
                     GENX(3DSTATE_STENCIL_BUFFER_length) +
                     GENX(3DSTATE_HIER_DEPTH_BUFFER_length) +
-                    GENX(3DSTATE_CLEAR_PARAMS_length)];
+                    GENX(3DSTATE_CLEAR_PARAMS_length) +
+                    GENX(MI_LOAD_REGISTER_IMM_length) * 2];
 };
 
 /**
@@ -5900,7 +5901,22 @@ iris_upload_dirty_render_state(struct iris_context *ice,
        * first.
        */
       uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4;
-      uint32_t cso_z_size = sizeof(cso_z->packets) - clear_length;
+      uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;;
+
+#if GEN_GEN == 12
+      /* GEN:BUG:14010455700
+       *
+       * ISL will change some CHICKEN registers depending on the depth surface
+       * format, along with emitting the depth and stencil packets. In that
+       * case, we want to do a depth flush and stall, so the pipeline is not
+       * using these settings while we change the registers.
+       */
+      iris_emit_end_of_pipe_sync(batch,
+                                 "Workaround: Stop pipeline for 14010455700",
+                                 PIPE_CONTROL_DEPTH_STALL |
+                                 PIPE_CONTROL_DEPTH_CACHE_FLUSH);
+#endif
+
       iris_batch_emit(batch, cso_z->packets, cso_z_size);
       if (GEN_GEN >= 12) {
          /* GEN:BUG:1408224581
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 6ed9ccc369e..127bc549a8b 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -7032,6 +7032,16 @@
     <field name="CL Primitives Count Report" start="0" end="63" type="uint"/>
   </register>
 
+  <register name="COMMON_SLICE_CHICKEN1" length="1" num="0x7010">
+    <field name="HIZ Plane Optimization disable bit" start="9" end="9" type="bool"/>
+    <field name="HIZ Plane Optimization disable bit Mask" start="25" end="25" type="bool"/>
+  </register>
+
+  <register name="HIZ_CHICKEN" length="1" num="0x7018">
+    <field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/>
+    <field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/>
+  </register>
+
   <register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304">
     <field name="PS Thread Panic Dispatch" start="6" end="7" type="uint"/>
     <field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/>
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 27b9073b180..d47313daf8e 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -223,6 +223,10 @@ isl_device_init(struct isl_device *dev,
       dev->ds.hiz_offset = 0;
    }
 
+   if (ISL_DEV_GEN(dev) >= 12) {
+      dev->ds.size += GEN12_MI_LOAD_REGISTER_IMM_length * 4 * 2;
+   }
+
    isl_device_setup_mocs(dev);
 }
 
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 4906d95a49c..782ca649156 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -255,6 +255,50 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
    GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
    dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
 
+#if GEN_GEN == 12
+   /* GEN:BUG:14010455700
+    *
+    * To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface
+    * Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.
+    */
+   bool enable_14010455700 =
+      info->depth_surf && info->depth_surf->samples == 1 &&
+      db.SurfaceType != SURFTYPE_NULL && db.SurfaceFormat == D16_UNORM;
+   struct GENX(COMMON_SLICE_CHICKEN1) chicken1 = {
+      .HIZPlaneOptimizationdisablebit = enable_14010455700,
+      .HIZPlaneOptimizationdisablebitMask = true,
+   };
+   uint32_t chicken1_dw;
+   GENX(COMMON_SLICE_CHICKEN1_pack)(NULL, &chicken1_dw, &chicken1);
+
+   struct GENX(MI_LOAD_REGISTER_IMM) lri = {
+      GENX(MI_LOAD_REGISTER_IMM_header),
+      .RegisterOffset = GENX(COMMON_SLICE_CHICKEN1_num),
+      .DataDWord = chicken1_dw,
+   };
+   GENX(MI_LOAD_REGISTER_IMM_pack)(NULL, dw, &lri);
+   dw += GENX(MI_LOAD_REGISTER_IMM_length);
+
+   /* GEN:BUG:1806527549
+    *
+    * Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM.
+    */
+   struct GENX(HIZ_CHICKEN) hiz_chicken = {
+      .HZDepthTestLEGEOptimizationDisable = db.SurfaceFormat == D16_UNORM,
+      .HZDepthTestLEGEOptimizationDisableMask = true,
+   };
+   uint32_t hiz_chicken_dw;
+   GENX(HIZ_CHICKEN_pack)(NULL, &hiz_chicken_dw, &hiz_chicken);
+
+   struct GENX(MI_LOAD_REGISTER_IMM) lri2 = {
+      GENX(MI_LOAD_REGISTER_IMM_header),
+      .RegisterOffset = GENX(HIZ_CHICKEN_num),
+      .DataDWord = hiz_chicken_dw,
+   };
+   GENX(MI_LOAD_REGISTER_IMM_pack)(NULL, dw, &lri2);
+   dw += GENX(MI_LOAD_REGISTER_IMM_length);
+#endif
+
    GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
    dw += GENX(3DSTATE_CLEAR_PARAMS_length);
 #endif
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 7e8c2d57eba..22d4f79d28d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -5160,8 +5160,6 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
       att_state->pending_load_aspects = 0;
    }
 
-   cmd_buffer_emit_depth_stencil(cmd_buffer);
-
 #if GEN_GEN >= 11
    /* The PIPE_CONTROL command description says:
     *
@@ -5175,6 +5173,23 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
       ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
       ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
 #endif
+
+#if GEN_GEN == 12
+   /* GEN:BUG:14010455700
+    *
+    * ISL will change some CHICKEN registers depending on the depth surface
+    * format, along with emitting the depth and stencil packets. In that case,
+    * we want to do a depth flush and stall, so the pipeline is not using these
+    * settings while we change the registers.
+    */
+   cmd_buffer->state.pending_pipe_bits |=
+      ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
+      ANV_PIPE_DEPTH_STALL_BIT |
+      ANV_PIPE_END_OF_PIPE_SYNC_BIT;
+   genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
+#endif
+
+   cmd_buffer_emit_depth_stencil(cmd_buffer);
 }
 
 static enum blorp_filter