diff options
| author | Jason Ekstrand <[email protected]> | 2015-09-09 13:55:39 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2015-09-15 11:13:48 -0700 |
| commit | c951bb83056724df02ba7e6fe2dfa720c0f45c1f (patch) | |
| tree | d4b79312eff8cd7b447cf1614a141d88fefbb0f5 /src | |
| parent | c3f8cde964f9850c86469a06d5eedf4e783cbf5c (diff) | |
i965/vec4_nir: Use partial SSA form rather than full non-SSA
We made this switch in the FS backend some time ago and it seems to make a
number of things a bit easier. In particular, supporting SSA values takes
very little work in the backend and allows us to take advantage of the
majority of the SSA information even after we've gotten rid of Phi nodes.
Reviewed-by: Eduardo Lima Mitev <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_nir.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 |
3 files changed, 20 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c index 8f3edc5cf01..f326b239d74 100644 --- a/src/mesa/drivers/dri/i965/brw_nir.c +++ b/src/mesa/drivers/dri/i965/brw_nir.c @@ -183,7 +183,7 @@ brw_create_nir(struct brw_context *brw, nir_print_shader(nir, stderr); } - nir_convert_from_ssa(nir, is_scalar); + nir_convert_from_ssa(nir, true); nir_validate_shader(nir); if (!is_scalar) { diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 01c6e8492c7..de74ec9bb68 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -423,6 +423,7 @@ public: virtual void nir_emit_alu(nir_alu_instr *instr); virtual void nir_emit_jump(nir_jump_instr *instr); virtual void nir_emit_texture(nir_tex_instr *instr); + virtual void nir_emit_undef(nir_ssa_undef_instr *instr); dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type); dst_reg get_nir_dest(nir_dest dest, nir_alu_type type); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 175d92b6b31..144f9e56eb7 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp @@ -367,6 +367,10 @@ vec4_visitor::nir_emit_instr(nir_instr *instr) nir_emit_texture(nir_instr_as_tex(instr)); break; + case nir_instr_type_ssa_undef: + nir_emit_undef(nir_instr_as_ssa_undef(instr)); + break; + default: fprintf(stderr, "VS instruction not yet implemented by NIR->vec4\n"); break; @@ -393,9 +397,14 @@ dst_reg_for_nir_reg(vec4_visitor *v, nir_register *nir_reg, dst_reg vec4_visitor::get_nir_dest(nir_dest dest) { - assert(!dest.is_ssa); - return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset, - dest.reg.indirect); + if (dest.is_ssa) { + dst_reg dst = dst_reg(GRF, alloc.allocate(1)); + nir_ssa_values[dest.ssa.index] = dst; + return dst; + } else { + return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset, + dest.reg.indirect); + } } dst_reg @@ -1529,4 +1538,10 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) mcs, is_cube_array, sampler, sampler_reg); } +void +vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr) +{ + nir_ssa_values[instr->def.index] = dst_reg(GRF, alloc.allocate(1)); +} + } |