i965/wm: Use stored hiz surface instead of creating copy

Now the last user of intel_miptree_get_aux_isl_surf() is gone.

Reviewed-by: Jason Ekstrand <[email protected]>
Signed-off-by: Topi Pohjolainen <[email protected]>

3 files changed, 2 insertions, 86 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 43c2aa49209..8f9a5e107d6 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -137,7 +137,7 @@ brw_emit_surface_state(struct brw_context *brw,
    union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
 
    struct brw_bo *aux_bo;
-   struct isl_surf *aux_surf = NULL, aux_surf_s;
+   struct isl_surf *aux_surf = NULL;
    uint64_t aux_offset = 0;
    enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
    if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) &&
@@ -151,8 +151,7 @@ brw_emit_surface_state(struct brw_context *brw,
          aux_bo = mt->mcs_buf->bo;
          aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
       } else {
-         intel_miptree_get_aux_isl_surf(brw, mt, aux_usage, &aux_surf_s);
-         aux_surf = &aux_surf_s;
+         aux_surf = &mt->hiz_buf->surf;
 
          aux_bo = mt->hiz_buf->bo;
          aux_offset = mt->hiz_buf->bo->offset64;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ca202c4e66e..abc7f989db8 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3728,80 +3728,3 @@ intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
 
    unreachable("Invalid MCS miptree");
 }
-
-/* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
- * USED FOR ANY REAL CALCULATIONS.  THE ONLY VALID USE OF SUCH A SURFACE IS TO
- * PASS IT INTO isl_surf_fill_state.
- */
-void
-intel_miptree_get_aux_isl_surf(struct brw_context *brw,
-                               const struct intel_mipmap_tree *mt,
-                               enum isl_aux_usage usage,
-                               struct isl_surf *surf)
-{
-   uint32_t aux_pitch, aux_qpitch;
-   if (mt->mcs_buf) {
-      aux_pitch = mt->mcs_buf->pitch;
-      aux_qpitch = mt->mcs_buf->qpitch;
-   } else if (mt->hiz_buf) {
-      aux_pitch = mt->hiz_buf->surf.row_pitch;
-      aux_qpitch = mt->hiz_buf->surf.array_pitch_el_rows;
-   } else {
-      return;
-   }
-
-   /* Start with a copy of the original surface. */
-   intel_miptree_get_isl_surf(brw, mt, surf);
-
-   /* Figure out the format and tiling of the auxiliary surface */
-   switch (usage) {
-   case ISL_AUX_USAGE_NONE:
-      unreachable("Invalid auxiliary usage");
-
-   case ISL_AUX_USAGE_HIZ:
-      isl_surf_get_hiz_surf(&brw->isl_dev, surf, surf);
-      break;
-
-   case ISL_AUX_USAGE_MCS:
-      /*
-       * From the SKL PRM:
-       *    "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
-       *    HALIGN 16 must be used."
-       */
-      if (brw->gen >= 9)
-         assert(mt->halign == 16);
-
-      isl_surf_get_mcs_surf(&brw->isl_dev, surf, surf);
-      break;
-
-   case ISL_AUX_USAGE_CCS_D:
-   case ISL_AUX_USAGE_CCS_E:
-      /*
-       * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
-       *
-       *    "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
-       *
-       * From the hardware spec for GEN9:
-       *
-       *    "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
-       *    HALIGN 16 must be used."
-       */
-      assert(mt->num_samples <= 1);
-      if (brw->gen >= 8)
-         assert(mt->halign == 16);
-
-      isl_surf_get_ccs_surf(&brw->isl_dev, surf, surf);
-      break;
-   }
-
-   /* We want the pitch of the actual aux buffer. */
-   surf->row_pitch = aux_pitch;
-
-   /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
-    * is in elements.  This doesn't match intel_mipmap_tree::qpitch which is
-    * in elements of the primary color surface so we have to divide by the
-    * compression block height.
-    */
-   surf->array_pitch_el_rows =
-      aux_qpitch / isl_format_get_layout(surf->format)->bh;
-}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 0a53319a0d6..a866f7aa608 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -765,12 +765,6 @@ intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
                                 const struct intel_mipmap_tree *mt);
 
 void
-intel_miptree_get_aux_isl_surf(struct brw_context *brw,
-                               const struct intel_mipmap_tree *mt,
-                               enum isl_aux_usage usage,
-                               struct isl_surf *surf);
-
-void
 intel_get_image_dims(struct gl_texture_image *image,
                      int *width, int *height, int *depth);