aboutsummaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
authorJason Ekstrand <[email protected]>2018-05-04 09:43:42 -0700
committerNanley Chery <[email protected]>2019-10-28 10:47:05 -0700
commitab994ecae68511f5f08f5ab0b5d4da624de3f7d9 (patch)
tree133da76a5617c2dd9caa9c0888561fe3c736e8e6 /src
parent6312328a61a372e78d246068ea0004868954a0aa (diff)
intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz
v2. Remove undocumented CCS_E-only mode for depth. (Nanley) Co-authored-by: Nanley Chery <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/intel/isl/isl_emit_depth_stencil.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 382c0ce22f5..e28ec836255 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -109,6 +109,11 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
db.SurfaceQPitch =
isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
#endif
+
+#if GEN_GEN >= 12
+ db.DepthBufferCompressionEnable =
+ info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS;
+#endif
}
#if GEN_GEN == 5 || GEN_GEN == 6
@@ -177,8 +182,11 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
};
assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
- info->hiz_usage == ISL_AUX_USAGE_HIZ);
- if (info->hiz_usage == ISL_AUX_USAGE_HIZ) {
+ info->hiz_usage == ISL_AUX_USAGE_HIZ ||
+ info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS);
+ if (info->hiz_usage == ISL_AUX_USAGE_HIZ ||
+ info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS) {
+ assert(GEN_GEN >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ);
db.HierarchicalDepthBufferEnable = true;
hiz.SurfaceBaseAddress = info->hiz_address;