diff options
| author | Samuel Pitoiset <[email protected]> | 2020-01-15 10:47:17 +0100 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-01-16 14:06:06 +0000 |
| commit | a445cb35bdf607857742a322576cd9763b1d67ea (patch) | |
| tree | 894a021f938d826746eb0c9140810a0f1ad2e341 /src | |
| parent | 923005bf5494264cddd0d7b886b43cb223c720b1 (diff) | |
aco: do not combine additions of DS instructions on GFX6
The offset field doesn't work as expected on GFX6.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3412>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/compiler/aco_optimizer.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index 224918c172f..d8e42d88b7d 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -787,7 +787,11 @@ void label_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr) DS_instruction *ds = static_cast<DS_instruction *>(instr.get()); Temp base; uint32_t offset; - if (i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && base.regClass() == instr->operands[i].regClass() && instr->opcode != aco_opcode::ds_swizzle_b32) { + bool has_usable_ds_offset = ctx.program->chip_class >= GFX7; + if (has_usable_ds_offset && + i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && + base.regClass() == instr->operands[i].regClass() && + instr->opcode != aco_opcode::ds_swizzle_b32) { if (instr->opcode == aco_opcode::ds_write2_b32 || instr->opcode == aco_opcode::ds_read2_b32 || instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) { if (offset % 4 == 0 && |