diff options
| author | Samuel Pitoiset <[email protected]> | 2020-01-16 17:02:44 +0100 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-01-20 16:24:55 +0000 |
| commit | 9e2fde84fca7824e32c6f12e87c1e9e1d3befb57 (patch) | |
| tree | e823ac8c1caf842047df59ed2fc554cba79e95b6 /src | |
| parent | fe9157a700341f38b448fa9279fb60d7e4a05b32 (diff) | |
aco: add new addr64 bit to MUBUF instructions on GFX6-GFX7
According to the different ISA docs (and to LLVM), this bit seems
to only exists on GFX6-GFX7.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-By: Timur Kristóf <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/compiler/aco_assembler.cpp | 3 | ||||
| -rw-r--r-- | src/amd/compiler/aco_ir.h | 1 | ||||
| -rw-r--r-- | src/amd/compiler/aco_opcodes.py | 1 | ||||
| -rw-r--r-- | src/amd/compiler/aco_print_ir.cpp | 2 |
4 files changed, 7 insertions, 0 deletions
diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp index dc341e59de0..241e3d44309 100644 --- a/src/amd/compiler/aco_assembler.cpp +++ b/src/amd/compiler/aco_assembler.cpp @@ -311,6 +311,9 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* encoding |= (mubuf->lds ? 1 : 0) << 16; encoding |= (mubuf->glc ? 1 : 0) << 14; encoding |= (mubuf->idxen ? 1 : 0) << 13; + assert(!mubuf->addr64 || ctx.chip_class <= GFX7); + if (ctx.chip_class == GFX6 || ctx.chip_class == GFX7) + encoding |= (mubuf->addr64 ? 1 : 0) << 15; encoding |= (mubuf->offen ? 1 : 0) << 12; if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) { assert(!mubuf->dlc); /* Device-level coherent is not supported on GFX9 and lower */ diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index 4239e5ffaf8..5fa9e1cb869 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -786,6 +786,7 @@ struct MUBUF_instruction : public Instruction { uint16_t offset : 12; /* Unsigned byte offset - 12 bit */ bool offen : 1; /* Supply an offset from VGPR (VADDR) */ bool idxen : 1; /* Supply an index from VGPR (VADDR) */ + bool addr64 : 1; /* SI, CIK: Address size is 64-bit */ bool glc : 1; /* globally coherent */ bool dlc : 1; /* NAVI: device level coherent */ bool slc : 1; /* system level coherent */ diff --git a/src/amd/compiler/aco_opcodes.py b/src/amd/compiler/aco_opcodes.py index 17520b7209f..db4a349bcb9 100644 --- a/src/amd/compiler/aco_opcodes.py +++ b/src/amd/compiler/aco_opcodes.py @@ -91,6 +91,7 @@ class Format(Enum): return [('unsigned', 'offset', None), ('bool', 'offen', None), ('bool', 'idxen', 'false'), + ('bool', 'addr64', 'false'), ('bool', 'disable_wqm', 'false'), ('bool', 'glc', 'false'), ('bool', 'dlc', 'false'), diff --git a/src/amd/compiler/aco_print_ir.cpp b/src/amd/compiler/aco_print_ir.cpp index 780980a8c69..81711a278c9 100644 --- a/src/amd/compiler/aco_print_ir.cpp +++ b/src/amd/compiler/aco_print_ir.cpp @@ -236,6 +236,8 @@ static void print_instr_format_specific(struct Instruction *instr, FILE *output) fprintf(output, " offen"); if (mubuf->idxen) fprintf(output, " idxen"); + if (mubuf->addr64) + fprintf(output, " addr64"); if (mubuf->glc) fprintf(output, " glc"); if (mubuf->dlc) |