diff options
| author | Samuel Pitoiset <[email protected]> | 2019-08-01 15:45:10 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-02 13:34:39 +0200 |
| commit | 856487a280f58bf2e7cf1d6a13c659375e6a3d5f (patch) | |
| tree | fe7321ed69d373b2a0dae52abb2e45e4f7736ba6 /src | |
| parent | e1c5d8a36490642dfa3891a3273f3830f3ac8161 (diff) | |
radv: only account for tile_swizzle for color surfaces with DCC
It's 0 for depth surfaces with TC compat HTILE enabled.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index f3237dd5985..221b554e73e 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -483,6 +483,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, meta_va = gpu_address + image->dcc_offset; if (chip_class <= GFX8) meta_va += base_level_info->dcc_offset; + + meta_va |= (uint32_t)plane->surface.tile_swizzle << 8; } else if (!is_storage_image && radv_image_is_tc_compat_htile(image)) { meta_va = gpu_address + image->htile_offset; @@ -490,10 +492,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, if (meta_va) { state[6] |= S_008F28_COMPRESSION_EN(1); - if (chip_class <= GFX9) { + if (chip_class <= GFX9) state[7] = meta_va >> 8; - state[7] |= plane->surface.tile_swizzle; - } } } |