diff options
| author | Marek Olšák <[email protected]> | 2019-07-05 17:30:08 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-19 20:16:19 -0400 |
| commit | 79d56e6a4a5337b8b671b999b14743051291e431 (patch) | |
| tree | 295251b0eebf258f4053a32245a2af0ca8744027 /src | |
| parent | a57f0f8a6baa118603a0241c38b9c26024da6049 (diff) | |
radeonsi/gfx10: implement ARB_post_depth_coverage
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_get.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 3 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index f2182a91076..b784d4ad0e9 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -163,6 +163,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_QUERY_SO_OVERFLOW: return sscreen->info.chip_class <= GFX9; + case PIPE_CAP_POST_DEPTH_COVERAGE: + return sscreen->info.chip_class >= GFX10; + case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: return !SI_BIG_ENDIAN && sscreen->info.has_userptr; @@ -224,7 +227,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_MUL_ZERO_WINS: case PIPE_CAP_UMA: case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: - case PIPE_CAP_POST_DEPTH_COVERAGE: case PIPE_CAP_TILE_RASTER_ORDER: case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: case PIPE_CAP_CONTEXT_PRIORITY_MASK: diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 14a3c3e0363..3f6e4828923 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -2880,6 +2880,9 @@ static void *si_create_shader_selector(struct pipe_context *ctx, sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); } + if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE]) + sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1); + (void) mtx_init(&sel->mutex, mtx_plain); si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready, |