diff options
| author | Daniel Schürmann <[email protected]> | 2020-06-23 11:55:34 +0100 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-06-24 10:52:28 +0000 |
| commit | 76b5d72921ced04fb8796b7a23a468fc1a4735e3 (patch) | |
| tree | 5d8194eefe8aed0c3d3ab326171d8a8e03632a3d /src | |
| parent | 91d7e40176328d0a256d9b9cf0ff749604035c51 (diff) | |
aco: align swap operations to 4 bytes on GFX6/7
GFX6/7 can only swap full registers
Reviewed-by: Rhys Perry <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5207>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/compiler/aco_lower_to_hw_instr.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp index 10ba9b82d3a..b208bb6fd34 100644 --- a/src/amd/compiler/aco_lower_to_hw_instr.cpp +++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp @@ -1159,7 +1159,7 @@ void do_swap(lower_context *ctx, Builder& bld, const copy_operation& copy, bool Definition op_as_def = Definition(op.physReg(), op.regClass()); if (ctx->program->chip_class >= GFX9 && def.regClass() == v1) { bld.vop1(aco_opcode::v_swap_b32, def, op_as_def, op, def_as_op); - } else if (def.regClass() == v1 || (def.regClass().is_subdword() && ctx->program->chip_class < GFX8)) { + } else if (def.regClass() == v1) { assert(def.physReg().byte() == 0 && op.physReg().byte() == 0); bld.vop2(aco_opcode::v_xor_b32, op_as_def, op, def_as_op); bld.vop2(aco_opcode::v_xor_b32, def, op, def_as_op); @@ -1561,6 +1561,10 @@ void handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context* swap.bytes = offset; } + /* GFX6-7 can only swap full registers */ + if (ctx->program->chip_class <= GFX7) + swap.bytes = align(swap.bytes, 4); + do_swap(ctx, bld, swap, preserve_scc, pi); /* remove from map */ |