diff options
| author | Samuel Pitoiset <[email protected]> | 2020-06-05 15:05:07 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2020-06-12 14:43:58 +0200 |
| commit | 54e7ae569bd703db2e3b8f060701e1677f104c69 (patch) | |
| tree | 56ec8bfc8f54be99933060524411f84544b37625 /src | |
| parent | 7b44f549b38a6866b50b34eb71922b026aed1d57 (diff) | |
radv/llvm: implement radv_enable_mrt_output_nan_fixup workaround
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5359>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_nir_to_llvm.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 4dd6ded5d02..e8ad6d83df3 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -1553,6 +1553,30 @@ si_llvm_init_export_args(struct radv_shader_context *ctx, break; } + /* Replace NaN by zero (only 32-bit) to fix game bugs if + * requested. + */ + if (ctx->args->options->enable_mrt_output_nan_fixup && + !is_16bit && + (col_format == V_028714_SPI_SHADER_32_R || + col_format == V_028714_SPI_SHADER_32_GR || + col_format == V_028714_SPI_SHADER_32_AR || + col_format == V_028714_SPI_SHADER_32_ABGR || + col_format == V_028714_SPI_SHADER_FP16_ABGR)) { + for (unsigned i = 0; i < 4; i++) { + LLVMValueRef args[2] = { + values[i], + LLVMConstInt(ctx->ac.i32, S_NAN | Q_NAN, false) + }; + LLVMValueRef isnan = + ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f32", ctx->ac.i1, + args, 2, AC_FUNC_ATTR_READNONE); + values[i] = LLVMBuildSelect(ctx->ac.builder, isnan, + ctx->ac.f32_0, + values[i], ""); + } + } + /* Pack f16 or norm_i16/u16. */ if (packf) { for (chan = 0; chan < 2; chan++) { |