diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-12 11:12:58 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-07-12 12:15:08 +0200 |
| commit | 4e38322dd83b8d3a7a107dabacf86739497db420 (patch) | |
| tree | a06336a5ab888563984563b9bd2c43d0c620c8d5 /src | |
| parent | 219d6939df8070bdc6e5054e71985a9d6d668da4 (diff) | |
radv/gfx10: fix wrong emission of GE_CNTL
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9b68650fd36..7720990ba45 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3461,7 +3461,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) && !radv_pipeline_has_gs(pipeline))); - radeon_set_context_reg(ctx_cs, R_03096C_GE_CNTL, + radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) | S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) | S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi)); |