diff options
| author | Dave Airlie <[email protected]> | 2014-11-18 10:55:44 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2014-11-18 11:59:30 +1000 |
| commit | 27e1e0e7108511b43d0f56f678c7201f39e2acc5 (patch) | |
| tree | c3158faaed37e22067b78c56cf0a1152505352f9 /src | |
| parent | 70dac5fa442a8c0cc8dfa2d8879c5c3c3dd885e4 (diff) | |
r600g/cayman: fix texture gather tests
It appears on cayman the TG4 outputs were reordered.
This fixes a lot of piglit tests.
Cc: "10.3 10.4" <[email protected]>
Reviewed-by: Glenn Kennard <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/r600/r600_shader.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 4c6ae4545ff..709fcd74471 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -5763,11 +5763,18 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX]; tex.inst_mod = texture_component_select; + if (ctx->bc->chip_class == CAYMAN) { /* GATHER4 result order is different from TGSI TG4 */ - tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; - tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; - tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; - tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; + tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7; + tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7; + tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7; + tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; + } else { + tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; + tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; + tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; + tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; + } } else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) { tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; |