diff options
author | Alyssa Rosenzweig <[email protected]> | 2019-09-28 09:48:53 -0400 |
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committer | Alyssa Rosenzweig <[email protected]> | 2019-09-30 08:40:13 -0400 |
commit | 2715bd02ee7e67a28ccf96ed24aeb8182bbef747 (patch) | |
tree | ffba87a41cd2480ff8ded09078feb56b2876138b /src | |
parent | 57bac68fffe4d7dcb5cf573ca9ad4cd262d3a5e1 (diff) |
pan/midgard: Schedule to smul/sadd
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Diffstat (limited to 'src')
-rw-r--r-- | src/panfrost/midgard/midgard_schedule.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index dfc02f1c337..ddd5edd7c84 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -753,6 +753,8 @@ mir_schedule_alu( unreachable("Bad condition"); } + mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL); + if (!writeout) mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT); @@ -777,6 +779,9 @@ mir_schedule_alu( unreachable("Bad condition"); } + /* Stage 2, let's schedule sadd before vmul for writeout */ + mir_choose_alu(&sadd, instructions, worklist, len, &predicate, UNIT_SADD); + /* Check if writeout reads its own register */ bool bad_writeout = false; |