diff options
| author | Lionel Landwerlin <[email protected]> | 2020-01-15 14:06:07 +0200 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-02-05 00:25:48 +0000 |
| commit | 19e7bcee1742a40981a0b1c06447bca22646c294 (patch) | |
| tree | 05f8872902569e1ee04308bcd2b2b271c972e2d4 /src | |
| parent | 2c07e03b792d57ae807a6953f0d8ff5f4bcdffd0 (diff) | |
iris: implement gen12 post sync pipe control workaround
Like Skylake, Gen12 requires a workaround for PIPE_CONTROLs using a
post-sync operation.
v2: Restrict to A0
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 7222e724ac6..db4568c7777 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6864,7 +6864,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, imm); } - if (GEN_GEN == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { + if ((GEN_GEN == 9 || (GEN_GEN == 12 && devinfo->revision == 0 /* A0*/)) && + IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { /* Project: SKL / Argument: LRI Post Sync Operation [23] * * "PIPECONTROL command with “Command Streamer Stall Enable” must be @@ -6873,6 +6874,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, * PIPELINE_SELECT command is set to GPGPU mode of operation)." * * The same text exists a few rows below for Post Sync Op. + * + * On Gen12 this is GEN:BUG:1607156449. */ iris_emit_raw_pipe_control(batch, "workaround: CS stall before gpgpu post-sync", |