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authorDave Airlie <[email protected]>2014-06-16 05:39:02 +0000
committerDave Airlie <[email protected]>2014-06-27 13:38:14 +1000
commit13eddf3bf2d9aee3ebca828d009c01d16f6545c6 (patch)
treebceb62f2274cf35ceb7e5ff36ff702efb1deb906 /src
parentdf282ce1bfd66ae75971b0e0e4fbf6f7b326d95c (diff)
nvc0: fix dri3 prime buffer creation
We need to place shared buffers into GART. Reviewed-by: Axel Davy <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
index 79c9390b78f..2f3cba8b879 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -296,7 +296,7 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
}
bo_config.nvc0.tile_mode = mt->level[0].tile_mode;
- if (!bo_config.nvc0.memtype && pt->usage == PIPE_USAGE_STAGING)
+ if (!bo_config.nvc0.memtype && (pt->usage == PIPE_USAGE_STAGING || pt->bind & PIPE_BIND_SHARED))
mt->base.domain = NOUVEAU_BO_GART;
else
mt->base.domain = NOUVEAU_BO_VRAM;