i965/gen6 depth surface: calculate minimum array element being rendered

(a23cfb8 for gen6)

In layered rendering this will be 0. Otherwise it will be the
selected slice.

Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>

2 files changed, 4 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 96825c67787..23e3aa266e5 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -807,6 +807,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
                                    NULL,
                                    &tile_mask_x, &tile_mask_y);
 
+   const unsigned min_array_element = params->depth.layer;
+
    lod = params->depth.level - params->depth.mt->first_level;
 
    /* 3DSTATE_DEPTH_BUFFER */
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 9e0357746b2..ec910f2bfe1 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -98,6 +98,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
       break;
    }
 
+   const unsigned min_array_element = irb ? irb->mt_layer : 0;
+
    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 
    BEGIN_BATCH(7);