i965: Port gen6+ 3DSTATE_VS to genxml.

Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)
v3:
   - Bring back some comments for gen6 and remove _NEW_TRANSFORM blocks
   from gen7+.

Signed-off-by: Rafael Antognolli <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>

6 files changed, 124 insertions, 304 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 7f25ae14d59..95d29acac5d 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -100,7 +100,6 @@ i965_FILES = \
 	gen7_te_state.c \
 	gen7_urb.c \
 	gen7_viewport_state.c \
-	gen7_vs_state.c \
 	gen7_wm_surface_state.c \
 	gen8_blend_state.c \
 	gen8_depth_state.c \
@@ -111,7 +110,6 @@ i965_FILES = \
 	gen8_multisample_state.c \
 	gen8_surface_state.c \
 	gen8_viewport_state.c \
-	gen8_vs_state.c \
 	hsw_queryobj.c \
 	hsw_sol.c \
 	intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index a87bf3a961b..72d63f67675 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -123,7 +123,6 @@ extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
-extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
@@ -136,7 +135,6 @@ extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
-extern const struct brw_tracked_state gen7_vs_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
-extern const struct brw_tracked_state gen8_vs_state;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
 
 static inline bool
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 17b8118d45f..b2d2306858d 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -68,116 +68,3 @@ const struct brw_tracked_state gen6_vs_push_constants = {
    },
    .emit = gen6_upload_vs_push_constants,
 };
-
-static void
-upload_vs_state(struct brw_context *brw)
-{
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   const struct brw_stage_state *stage_state = &brw->vs.base;
-   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-   const struct brw_vue_prog_data *vue_prog_data =
-      brw_vue_prog_data(stage_state->prog_data);
-   uint32_t floating_point_mode = 0;
-
-   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
-    * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
-    *
-    *   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
-    *   command that causes the VS Function Enable to toggle. Pipeline
-    *   flush can be executed by sending a PIPE_CONTROL command with CS
-    *   stall bit set and a post sync operation.
-    *
-    * We've already done such a flush at the start of state upload, so we
-    * don't need to do another one here.
-    */
-
-   if (stage_state->push_const_size == 0) {
-      /* Disable the push constant buffers. */
-      BEGIN_BATCH(5);
-      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      BEGIN_BATCH(5);
-      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
-		GEN6_CONSTANT_BUFFER_0_ENABLE |
-		(5 - 2));
-      /* Pointer to the VS constant buffer.  Covered by the set of
-       * state flags from gen6_upload_vs_constants
-       */
-      OUT_BATCH(stage_state->push_const_offset +
-		stage_state->push_const_size - 1);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   }
-
-   if (prog_data->use_alt_mode)
-      floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
-
-   BEGIN_BATCH(6);
-   OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
-   OUT_BATCH(stage_state->prog_offset);
-   OUT_BATCH(floating_point_mode |
-	     ((ALIGN(stage_state->sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT) |
-             ((prog_data->binding_table.size_bytes / 4) <<
-              GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
-
-   if (prog_data->total_scratch) {
-      OUT_RELOC(stage_state->scratch_bo,
-		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-		ffs(stage_state->per_thread_scratch) - 11);
-   } else {
-      OUT_BATCH(0);
-   }
-
-   OUT_BATCH((prog_data->dispatch_grf_start_reg <<
-              GEN6_VS_DISPATCH_START_GRF_SHIFT) |
-	     (vue_prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
-	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
-
-   OUT_BATCH(((devinfo->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
-	     GEN6_VS_STATISTICS_ENABLE |
-	     GEN6_VS_ENABLE);
-   ADVANCE_BATCH();
-
-   /* Based on my reading of the simulator, the VS constants don't get
-    * pulled into the VS FF unit until an appropriate pipeline flush
-    * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
-    * references to them into a little FIFO.  The flushes are common,
-    * but don't reliably happen between this and a 3DPRIMITIVE, causing
-    * the primitive to use the wrong constants.  Then the FIFO
-    * containing the constant setup gets added to again on the next
-    * constants change, and eventually when a flush does happen the
-    * unit is overwhelmed by constant changes and dies.
-    *
-    * To avoid this, send a PIPE_CONTROL down the line that will
-    * update the unit immediately loading the constants.  The flush
-    * type bits here were those set by the STATE_BASE_ADDRESS whose
-    * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
-    * bug reports that led to this workaround, and may be more than
-    * what is strictly required to avoid the issue.
-    */
-   brw_emit_pipe_control_flush(brw,
-                               PIPE_CONTROL_DEPTH_STALL |
-                               PIPE_CONTROL_INSTRUCTION_INVALIDATE |
-                               PIPE_CONTROL_STATE_CACHE_INVALIDATE);
-}
-
-const struct brw_tracked_state gen6_vs_state = {
-   .dirty = {
-      .mesa  = _NEW_PROGRAM_CONSTANTS |
-               _NEW_TRANSFORM,
-      .brw   = BRW_NEW_BATCH |
-               BRW_NEW_BLORP |
-               BRW_NEW_CONTEXT |
-               BRW_NEW_PUSH_CONSTANT_ALLOCATION |
-               BRW_NEW_VERTEX_PROGRAM |
-               BRW_NEW_VS_PROG_DATA,
-   },
-   .emit = upload_vs_state,
-};
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
deleted file mode 100644
index 623c78471fa..00000000000
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_vs_state(struct brw_context *brw)
-{
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   const struct brw_stage_state *stage_state = &brw->vs.base;
-   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-   const struct brw_vue_prog_data *vue_prog_data =
-      brw_vue_prog_data(stage_state->prog_data);
-   uint32_t floating_point_mode = 0;
-   const int max_threads_shift = brw->is_haswell ?
-      HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
-
-   if (!brw->is_haswell && !brw->is_baytrail)
-      gen7_emit_vs_workaround_flush(brw);
-
-   if (prog_data->use_alt_mode)
-      floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
-
-   BEGIN_BATCH(6);
-   OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
-   OUT_BATCH(stage_state->prog_offset);
-   OUT_BATCH(floating_point_mode |
-	     ((ALIGN(stage_state->sampler_count, 4)/4) <<
-              GEN6_VS_SAMPLER_COUNT_SHIFT) |
-             ((prog_data->binding_table.size_bytes / 4) <<
-              GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
-
-   if (prog_data->total_scratch) {
-      OUT_RELOC(stage_state->scratch_bo,
-		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-		ffs(stage_state->per_thread_scratch) - 11);
-   } else {
-      OUT_BATCH(0);
-   }
-
-   OUT_BATCH((prog_data->dispatch_grf_start_reg <<
-              GEN6_VS_DISPATCH_START_GRF_SHIFT) |
-	     (vue_prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
-	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
-
-   OUT_BATCH(((devinfo->max_vs_threads - 1) << max_threads_shift) |
-	     GEN6_VS_STATISTICS_ENABLE |
-	     GEN6_VS_ENABLE);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen7_vs_state = {
-   .dirty = {
-      .mesa  = 0,
-      .brw   = BRW_NEW_BATCH |
-               BRW_NEW_BLORP |
-               BRW_NEW_CONTEXT |
-               BRW_NEW_VS_PROG_DATA,
-   },
-   .emit = upload_vs_state,
-};
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
deleted file mode 100644
index 7b66da4b17c..00000000000
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_vs_state(struct brw_context *brw)
-{
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   const struct brw_stage_state *stage_state = &brw->vs.base;
-   uint32_t floating_point_mode = 0;
-
-   /* BRW_NEW_VS_PROG_DATA */
-   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-   const struct brw_vue_prog_data *vue_prog_data =
-      brw_vue_prog_data(stage_state->prog_data);
-
-   assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
-          vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
-
-   if (prog_data->use_alt_mode)
-      floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
-
-   BEGIN_BATCH(9);
-   OUT_BATCH(_3DSTATE_VS << 16 | (9 - 2));
-   OUT_BATCH(stage_state->prog_offset);
-   OUT_BATCH(0);
-   OUT_BATCH(floating_point_mode |
-             ((ALIGN(stage_state->sampler_count, 4) / 4) <<
-               GEN6_VS_SAMPLER_COUNT_SHIFT) |
-             ((prog_data->binding_table.size_bytes / 4) <<
-               GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
-
-   if (prog_data->total_scratch) {
-      OUT_RELOC64(stage_state->scratch_bo,
-                  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                  ffs(stage_state->per_thread_scratch) - 11);
-   } else {
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-   }
-
-   OUT_BATCH((prog_data->dispatch_grf_start_reg <<
-              GEN6_VS_DISPATCH_START_GRF_SHIFT) |
-             (vue_prog_data->urb_read_length <<
-              GEN6_VS_URB_READ_LENGTH_SHIFT) |
-             (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
-
-   uint32_t simd8_enable =
-      vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ?
-      GEN8_VS_SIMD8_ENABLE : 0;
-   OUT_BATCH(((devinfo->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
-             GEN6_VS_STATISTICS_ENABLE |
-             simd8_enable |
-             GEN6_VS_ENABLE);
-
-   OUT_BATCH(vue_prog_data->cull_distance_mask);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen8_vs_state = {
-   .dirty = {
-      .mesa  = 0,
-      .brw   = BRW_NEW_BATCH |
-               BRW_NEW_BLORP |
-               BRW_NEW_CONTEXT |
-               BRW_NEW_VS_PROG_DATA,
-   },
-   .emit = upload_vs_state,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 36f5d320658..2ff809f6fa0 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -27,6 +27,9 @@
 #include "genxml/gen_macros.h"
 
 #include "brw_context.h"
+#if GEN_GEN == 6
+#include "brw_defines.h"
+#endif
 #include "brw_state.h"
 #include "brw_wm.h"
 #include "brw_util.h"
@@ -954,6 +957,124 @@ static const struct brw_tracked_state genX(wm_state) = {
    .emit = genX(upload_wm),
 };
 
+/* ---------------------------------------------------------------------- */
+
+#define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
+   pkt.KernelStartPointer = stage_state->prog_offset;                     \
+   pkt.SamplerCount       =                                               \
+      DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);          \
+   pkt.BindingTableEntryCount =                                           \
+      stage_prog_data->binding_table.size_bytes / 4;                      \
+   pkt.FloatingPointMode  = stage_prog_data->use_alt_mode;                \
+                                                                          \
+   if (stage_prog_data->total_scratch) {                                  \
+      pkt.ScratchSpaceBasePointer =                                       \
+         render_bo(stage_state->scratch_bo, 0);                           \
+      pkt.PerThreadScratchSpace =                                         \
+         ffs(stage_state->per_thread_scratch) - 11;                       \
+   }                                                                      \
+                                                                          \
+   pkt.DispatchGRFStartRegisterForURBData =                               \
+      stage_prog_data->dispatch_grf_start_reg;                            \
+   pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length;       \
+   pkt.prefix##URBEntryReadOffset = 0;                                    \
+                                                                          \
+   pkt.StatisticsEnable = true;                                           \
+   pkt.Enable           = true;
+
+
+static void
+genX(upload_vs_state)(struct brw_context *brw)
+{
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
+   const struct brw_stage_state *stage_state = &brw->vs.base;
+
+   /* BRW_NEW_VS_PROG_DATA */
+   const struct brw_vue_prog_data *vue_prog_data =
+      brw_vue_prog_data(brw->vs.base.prog_data);
+   const struct brw_stage_prog_data *stage_prog_data = &vue_prog_data->base;
+
+   assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
+          vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
+
+   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
+    * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
+    *
+    *   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
+    *   command that causes the VS Function Enable to toggle. Pipeline
+    *   flush can be executed by sending a PIPE_CONTROL command with CS
+    *   stall bit set and a post sync operation.
+    *
+    * We've already done such a flush at the start of state upload, so we
+    * don't need to do another one here.
+    */
+
+#if GEN_GEN < 7
+   brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), cvs) {
+      if (stage_state->push_const_size != 0) {
+         cvs.Buffer0Valid = true;
+         cvs.PointertoVSConstantBuffer0 = stage_state->push_const_offset;
+         cvs.VSConstantBuffer0ReadLength = stage_state->push_const_size - 1;
+      }
+   }
+#endif
+
+   if (GEN_GEN == 7 && devinfo->is_ivybridge)
+      gen7_emit_vs_workaround_flush(brw);
+
+   brw_batch_emit(brw, GENX(3DSTATE_VS), vs) {
+      INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
+
+      vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
+
+#if GEN_GEN >= 8
+      vs.SIMD8DispatchEnable =
+         vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
+
+      vs.UserClipDistanceCullTestEnableBitmask =
+         vue_prog_data->cull_distance_mask;
+#endif
+   }
+
+#if GEN_GEN < 7
+   /* Based on my reading of the simulator, the VS constants don't get
+    * pulled into the VS FF unit until an appropriate pipeline flush
+    * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
+    * references to them into a little FIFO.  The flushes are common,
+    * but don't reliably happen between this and a 3DPRIMITIVE, causing
+    * the primitive to use the wrong constants.  Then the FIFO
+    * containing the constant setup gets added to again on the next
+    * constants change, and eventually when a flush does happen the
+    * unit is overwhelmed by constant changes and dies.
+    *
+    * To avoid this, send a PIPE_CONTROL down the line that will
+    * update the unit immediately loading the constants.  The flush
+    * type bits here were those set by the STATE_BASE_ADDRESS whose
+    * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
+    * bug reports that led to this workaround, and may be more than
+    * what is strictly required to avoid the issue.
+    */
+   brw_emit_pipe_control_flush(brw,
+                               PIPE_CONTROL_DEPTH_STALL |
+                               PIPE_CONTROL_INSTRUCTION_INVALIDATE |
+                               PIPE_CONTROL_STATE_CACHE_INVALIDATE);
+#endif
+}
+
+static const struct brw_tracked_state genX(vs_state) = {
+   .dirty = {
+      .mesa  = (GEN_GEN < 7 ? (_NEW_PROGRAM_CONSTANTS | _NEW_TRANSFORM) : 0),
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_BLORP |
+               BRW_NEW_CONTEXT |
+               BRW_NEW_VS_PROG_DATA |
+               (GEN_GEN < 7 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION |
+                              BRW_NEW_VERTEX_PROGRAM
+                            : 0),
+   },
+   .emit = genX(upload_vs_state),
+};
+
 #endif
 
 /* ---------------------------------------------------------------------- */
@@ -1825,7 +1946,7 @@ genX(init_atoms)(struct brw_context *brw)
       &gen6_sampler_state,
       &gen6_multisample_state,
 
-      &gen6_vs_state,
+      &genX(vs_state),
       &gen6_gs_state,
       &genX(clip_state),
       &genX(sf_state),
@@ -1909,7 +2030,7 @@ genX(init_atoms)(struct brw_context *brw)
       &brw_gs_samplers,
       &gen6_multisample_state,
 
-      &gen7_vs_state,
+      &genX(vs_state),
       &gen7_hs_state,
       &gen7_te_state,
       &gen7_ds_state,
@@ -1996,7 +2117,7 @@ genX(init_atoms)(struct brw_context *brw)
       &brw_gs_samplers,
       &gen8_multisample_state,
 
-      &gen8_vs_state,
+      &genX(vs_state),
       &gen8_hs_state,
       &gen7_te_state,
       &gen8_ds_state,