diff options
| author | Michel Dänzer <[email protected]> | 2012-08-28 20:06:20 +0200 |
|---|---|---|
| committer | Michel Dänzer <[email protected]> | 2012-08-28 20:26:50 +0200 |
| commit | 16e42a5dd065c09f6d561537009639906b22ce45 (patch) | |
| tree | b976e590a313aaf5b52af1d2cf6f646b406f8802 /src | |
| parent | 6ca64393c9f357160c8439bf7e73610641c6ded2 (diff) | |
radeon/llvm: Basic support for SI EXEC register.
Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIGenRegisterInfo.pl | 7 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 15 |
3 files changed, 23 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp b/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp index 1f36105b251..eeb8d265f7e 100644 --- a/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp +++ b/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp @@ -81,6 +81,9 @@ void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) { VCCUsed = true; continue; } + if (reg == AMDGPU::EXEC) { + continue; + } if (AMDGPU::SReg_32RegClass.contains(reg)) { isSGPR = true; width = 1; diff --git a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl index 110c04f22fd..dd0efcc462f 100644 --- a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl +++ b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl @@ -88,6 +88,7 @@ class SGPR_256 <bits<8> num, string name, list<Register> subregs> : SI_256 <name, subregs>; def VCC : SIReg<"VCC">; +def EXEC : SIReg<"EXEC">; def SCC : SIReg<"SCC">; def SREG_LIT_0 : SIReg <"S LIT 0">; @@ -169,6 +170,7 @@ def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>; def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>; +def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>; STRING @@ -271,6 +273,11 @@ sub print_reg_class { push (@registers, 'VCC') } + #Add EXEC to SReg_64 + if ($class_prefix eq 'SReg' and $reg_width == 64) { + push (@registers, 'EXEC') + } + my $reg_list = join(', ', @registers); print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n"; diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 304732178c6..ee4c8f5a36f 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -630,8 +630,19 @@ def S_CBRANCH_VCCNZ : SOPP < "S_CBRANCH_VCCNZ", [] >; -//def S_CBRANCH_EXECZ : SOPP_ <0x00000008, "S_CBRANCH_EXECZ", []>; -//def S_CBRANCH_EXECNZ : SOPP_ <0x00000009, "S_CBRANCH_EXECNZ", []>; + +let DisableEncoding = "$exec" in { +def S_CBRANCH_EXECZ : SOPP < + 0x00000008, (ins brtarget:$target, EXECReg:$exec), + "S_CBRANCH_EXECZ", + [] +>; +def S_CBRANCH_EXECNZ : SOPP < + 0x00000009, (ins brtarget:$target, EXECReg:$exec), + "S_CBRANCH_EXECNZ", + [] +>; +} // End DisableEncoding = "$exec" } // End isBranch = 1 |