i965/fs: Refactor sampler message header to duplicate less code.

Previously, the code to copy g0 to the message header existed in two
places - one for the texture offset case, and one for any other case.

By treating texture_offset as a special case of header_present, we can
remove this duplication and shorten the code.  Future patches which add
new header fields also won't have to add additional duplication.

This also clarifies a confusing construct.  The old code contained:

   } else if (inst->header_present) {
      if (brw->gen >= 7) {
         ...explicit copy from g0 to the message header...
      } else {
         /* Set up an implied move from g0 to the MRF. */
      }
   }

This looks like it might set up an implied move on Sandybridge, which
doesn't support those.  However, Sandybridge only uses a message header
for texture offsets, so it would never hit this code path.  The new code
avoids this implicit knowledge by only setting up an implied move on
Gen4-5.

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Reviewed-by: Chris Forbes <[email protected]>

1 files changed, 21 insertions, 25 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index efccd924a04..38c7c5c5e5e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -534,36 +534,32 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
     * we need to set it up explicitly and load the offset bitfield.
     * Otherwise, we can use an implied move from g0 to the first message reg.
     */
-   if (inst->texture_offset) {
-      struct brw_reg header_reg;
-
-      if (brw->gen >= 7) {
-         header_reg = src;
+   if (inst->header_present) {
+      if (brw->gen < 6 && !inst->texture_offset) {
+         /* Set up an implied move from g0 to the MRF. */
+         src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
       } else {
-         assert(inst->base_mrf != -1);
-         header_reg = brw_message_reg(inst->base_mrf);
-      }
-      brw_push_insn_state(p);
-      brw_set_mask_control(p, BRW_MASK_DISABLE);
-      brw_set_compression_control(p, BRW_COMPRESSION_NONE);
-      /* Explicitly set up the message header by copying g0 to the MRF. */
-      brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
-
-      /* Then set the offset bits in DWord 2. */
-      brw_MOV(p, get_element_ud(header_reg, 2),
-                 brw_imm_ud(inst->texture_offset));
-      brw_pop_insn_state(p);
-   } else if (inst->header_present) {
-      if (brw->gen >= 7) {
-         /* Explicitly set up the message header by copying g0 to the MRF. */
+         struct brw_reg header_reg;
+
+         if (brw->gen >= 7) {
+            header_reg = src;
+         } else {
+            assert(inst->base_mrf != -1);
+            header_reg = brw_message_reg(inst->base_mrf);
+         }
+
          brw_push_insn_state(p);
          brw_set_mask_control(p, BRW_MASK_DISABLE);
          brw_set_compression_control(p, BRW_COMPRESSION_NONE);
-         brw_MOV(p, src, brw_vec8_grf(0, 0));
+         /* Explicitly set up the message header by copying g0 to the MRF. */
+         brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
+
+         if (inst->texture_offset) {
+            /* Set the offset bits in DWord 2. */
+            brw_MOV(p, get_element_ud(header_reg, 2),
+                       brw_imm_ud(inst->texture_offset));
+         }
          brw_pop_insn_state(p);
-      } else {
-         /* Set up an implied move from g0 to the MRF. */
-         src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
       }
    }