diff options
| author | Tom Stellard <[email protected]> | 2012-09-06 15:41:59 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-09-11 14:53:47 -0400 |
| commit | d3e58f75d257eefd18e1830573487830a40caf12 (patch) | |
| tree | 131f4d27bf7699ef39f4fa9a8214fcac0f577781 /src | |
| parent | 5fff032dd513c74e4fdd2ac04197f09531720c77 (diff) | |
radeonsi: Move interpolation mode check into the compiler
The compiler needs to know which interpolation modes are enabled, so
it knows which values will be preloaded into the VGPRs.
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/SIAssignInterpRegs.cpp | 13 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 20 |
2 files changed, 21 insertions, 12 deletions
diff --git a/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp b/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp index 447eff6f5ac..0e36e6b8b78 100644 --- a/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp +++ b/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp @@ -52,6 +52,7 @@ public: char SIAssignInterpRegsPass::ID = 0; #define INTERP_VALUES 16 +#define REQUIRED_VALUE_MAX_INDEX 7 struct interp_info { bool enabled; @@ -92,16 +93,26 @@ bool SIAssignInterpRegsPass::runOnMachineFunction(MachineFunction &MF) return false; } MachineRegisterInfo &MRI = MF.getRegInfo(); + bool ForceEnable = true; /* First pass, mark the interpolation values that are used. */ for (unsigned interp_idx = 0; interp_idx < INTERP_VALUES; interp_idx++) { for (unsigned reg_idx = 0; reg_idx < InterpUse[interp_idx].reg_count; reg_idx++) { - InterpUse[interp_idx].enabled = + InterpUse[interp_idx].enabled = InterpUse[interp_idx].enabled || !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]); + if (InterpUse[interp_idx].enabled && + interp_idx <= REQUIRED_VALUE_MAX_INDEX) { + ForceEnable = false; + } } } + // At least one interpolation mode must be enabled or else the GPU will hang. + if (ForceEnable) { + InterpUse[0].enabled = true; + } + unsigned used_vgprs = 0; /* Second pass, replace with VGPRs. */ diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 8f6dde04431..8b43f5a8f7d 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -170,17 +170,15 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); spi_ps_input_ena = shader->spi_ps_input_ena; /* we need to enable at least one of them, otherwise we hang the GPU */ - if (!G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) && - !G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) && - !G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) && - !G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) && - !G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) && - !G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) && - !G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) && - !G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena)) { - - spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1); - } + assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) || + G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || + G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || + G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) || + G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) || + G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) || + G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) || + G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena)); + si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena); si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena); si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control); |