diff options
| author | Eric Anholt <[email protected]> | 2013-06-20 15:41:24 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-06-28 13:35:24 -0700 |
| commit | a40f9871a04ba45e0eac0b86ad4cae2e06e1e0bb (patch) | |
| tree | 3f028c10976de60902832be898394d311c1b63c2 /src | |
| parent | 173666e2ed7ed71ae7aafa1780aa44d90ef7cb4a (diff) | |
i915: Drop unused register #defines from the shared reg file.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_reg.h | 67 |
1 files changed, 0 insertions, 67 deletions
diff --git a/src/mesa/drivers/dri/i915/intel_reg.h b/src/mesa/drivers/dri/i915/intel_reg.h index dd91a1586c7..2e355a8bc84 100644 --- a/src/mesa/drivers/dri/i915/intel_reg.h +++ b/src/mesa/drivers/dri/i915/intel_reg.h @@ -55,36 +55,6 @@ #define _3DSTATE_DRAWRECT_INFO (CMD_3D | (0x1d<<24) | (0x80<<16) | 0x3) -/** @{ - * - * PIPE_CONTROL operation, a combination MI_FLUSH and register write with - * additional flushing control. - */ -#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24)) -#define PIPE_CONTROL_CS_STALL (1 << 20) -#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19) -#define PIPE_CONTROL_TLB_INVALIDATE (1 << 18) -#define PIPE_CONTROL_SYNC_GFDT (1 << 17) -#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1 << 16) -#define PIPE_CONTROL_NO_WRITE (0 << 14) -#define PIPE_CONTROL_WRITE_IMMEDIATE (1 << 14) -#define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14) -#define PIPE_CONTROL_WRITE_TIMESTAMP (3 << 14) -#define PIPE_CONTROL_DEPTH_STALL (1 << 13) -#define PIPE_CONTROL_WRITE_FLUSH (1 << 12) -#define PIPE_CONTROL_INSTRUCTION_FLUSH (1 << 11) -#define PIPE_CONTROL_TC_FLUSH (1 << 10) /* GM45+ only */ -#define PIPE_CONTROL_ISP_DIS (1 << 9) -#define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8) -/* GT */ -#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4) -#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3) -#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2) -#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) -#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) -#define PIPE_CONTROL_PPGTT_WRITE (0 << 2) -#define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2) - /** @} */ /** @{ @@ -261,40 +231,3 @@ #define BR13_8 (0x0 << 24) #define BR13_565 (0x1 << 24) #define BR13_8888 (0x3 << 24) - -#define FENCE_LINEAR 0 -#define FENCE_XMAJOR 1 -#define FENCE_YMAJOR 2 - -/* Pipeline Statistics Counter Registers */ -#define IA_VERTICES_COUNT 0x2310 -#define IA_PRIMITIVES_COUNT 0x2318 -#define VS_INVOCATION_COUNT 0x2320 -#define HS_INVOCATION_COUNT 0x2300 -#define DS_INVOCATION_COUNT 0x2308 -#define GS_INVOCATION_COUNT 0x2328 -#define GS_PRIMITIVES_COUNT 0x2330 -#define CL_INVOCATION_COUNT 0x2338 -#define CL_PRIMITIVES_COUNT 0x2340 -#define PS_INVOCATION_COUNT 0x2348 -#define PS_DEPTH_COUNT 0x2350 - -#define SO_NUM_PRIM_STORAGE_NEEDED 0x2280 -#define SO_PRIM_STORAGE_NEEDED0_IVB 0x5240 -#define SO_PRIM_STORAGE_NEEDED1_IVB 0x5248 -#define SO_PRIM_STORAGE_NEEDED2_IVB 0x5250 -#define SO_PRIM_STORAGE_NEEDED3_IVB 0x5258 - -#define SO_NUM_PRIMS_WRITTEN 0x2288 -#define SO_NUM_PRIMS_WRITTEN0_IVB 0x5200 -#define SO_NUM_PRIMS_WRITTEN1_IVB 0x5208 -#define SO_NUM_PRIMS_WRITTEN2_IVB 0x5210 -#define SO_NUM_PRIMS_WRITTEN3_IVB 0x5218 - -#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) - -#define TIMESTAMP 0x2358 - -#define BCS_SWCTRL 0x22200 -# define BCS_SWCTRL_SRC_Y (1 << 0) -# define BCS_SWCTRL_DST_Y (1 << 1) |