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authorBrian <[email protected]>2008-01-23 15:39:34 -0700
committerBrian <[email protected]>2008-01-23 15:39:34 -0700
commit1cf3c77e086d3f8b01921aae9b7309aa62b3d15e (patch)
treeb5ea7de7acb276771257662c8ad0839ed2a46c75 /src
parent336e2cb9ec52e5cf8b2fac3142d5a67e3dcd55c4 (diff)
gallium: in sp_tile_cache_clear() mark all cache slots as empty/free. Fixes progs/redbook/stencil.c
Diffstat (limited to 'src')
-rw-r--r--src/mesa/pipe/softpipe/sp_tile_cache.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/pipe/softpipe/sp_tile_cache.c b/src/mesa/pipe/softpipe/sp_tile_cache.c
index 1974f774591..bc7e8d01e41 100644
--- a/src/mesa/pipe/softpipe/sp_tile_cache.c
+++ b/src/mesa/pipe/softpipe/sp_tile_cache.c
@@ -538,6 +538,7 @@ void
sp_tile_cache_clear(struct softpipe_tile_cache *tc, uint clearValue)
{
uint r, g, b, a;
+ uint pos;
tc->clear_val = clearValue;
@@ -576,4 +577,9 @@ sp_tile_cache_clear(struct softpipe_tile_cache *tc, uint clearValue)
/* disable the optimization */
memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
#endif
+
+ for (pos = 0; pos < NUM_ENTRIES; pos++) {
+ struct softpipe_cached_tile *tile = tc->entries + pos;
+ tile->x = tile->y = -1;
+ }
}